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set_clock_groups -asynchronous tells static timing analysis that clocks in different groups have no known phase relationship, so ordinary timing paths between those groups are not analyzed in either direction. It does not make signals crossing between the domains safe: the design still needs appropriate clock-domain-crossing (CDC) logic, and some CDC paths may need separate skew or net-delay constraints.
What the asynchronous clock-group constraint does
In SDC, a clock group defines a timing relationship. Marking groups asynchronous tells the timing tool not to analyze ordinary setup and hold paths from one group to another, or in the reverse direction. Paths between clocks in the same group remain subject to timing analysis.
For two unrelated clocks, a basic form is:
set_clock_groups -asynchronous
-group {clk_a}
-group {clk_b}AMD’s Vivado Design Suite Tcl Command Reference Guide UG835 (2024) describes asynchronous clocks as having “no known phase relationship,” typically because they do not share a primary clock or a common period. Intel’s Quartus command reference (2025) describes clock groups as a way to specify which clocks are not related. These definitions concern timing relationships; they do not certify the safety of a clock-domain crossing.
Choose the relationship that matches the clocks
Do not use an asynchronous relationship merely because two clocks have different names or frequencies. Choose based on whether the clocks can run together and whether their timing relationship is meaningful.
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| Relationship | Can both clocks run at once? | Phase relationship | Clock-tree situation and typical use | Generated clocks | Tool-specific caveat |
|---|---|---|---|---|---|
| Asynchronous | Yes | No known deterministic relationship | Independent or unrelated sources, such as separate oscillator domains or FIFO read and write clocks | Include derived clocks when the intent is to make the whole derived tree asynchronous to the other group | Timing between groups is cut; CDC-specific checks and constraints may still be needed |
| Logically exclusive | No; only one is active in the design at a time | Not applicable while both are active, because they are mutually selected | Alternative clocks selected by a mux | Group the relevant clocks according to the intended exclusive relationship | Use for logical mutual exclusion, not simply because clocks are unrelated |
| Physically exclusive | No; the clocks cannot physically coexist on the device | Not applicable | Alternative sources that use the same physical clock pin | Group the relevant clocks according to the intended physical relationship | Crosstalk and signal-integrity treatment may vary by tool and version |
The distinction between logical and physical exclusivity matters: a mux can make clocks mutually exclusive in the design, while physical exclusivity means the clock trees cannot coexist on the device. For a specific tool and version, confirm how the chosen exclusivity setting affects timing and signal-integrity analysis.
Include generated clocks when the whole derived tree is asynchronous
A generated clock is derived from another clock, but it may still need to be grouped explicitly to express the intended relationship between complete clock domains. AMD documents this Vivado form:
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set_clock_groups
-group [get_clocks -include_generated_clocks src_clk]
-group [get_clocks -include_generated_clocks sync_clk]
-asynchronousThe -include_generated_clocks option includes clocks derived from each named clock. AMD notes that this prevents those derived clocks from being timed against the other master domain. Use this form when the whole derived tree is meant to be asynchronous; do not assume that naming only a master clock expresses every intended relationship.
Understand the scope before applying a group
With multiple -group options, clocks in each group are cut from clocks in every other group. Clocks listed in the same group are not cut from each other by this constraint.
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Vivado also supports a single-group form. In AMD’s documented behavior, that group is cut from all other clocks in the design, including clocks created later. This broad scope can unintentionally suppress timing for a subsequently added domain. Prefer enumerating the intended groups when that better communicates the design intent, and inspect the resolved clock collections and timing reports after loading constraints.
The asynchronous group constraint is broadly equivalent to bidirectional false paths between the grouped clocks. It is not a blanket instruction to ignore every timing check associated with the crossing: architecture-specific constraints, such as skew or net-delay limits, may still be necessary.
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Apply and review the constraint
- Define clocks first. Create the primary and generated clocks before applying clock groups so the intended clocks exist for collection and constraint resolution.
- Resolve the intended clocks. In Vivado, check the results of each
get_clockscollection. In Quartus, use the equivalent clock collection mechanism for the project. Confirm that each intended clock is included and that no unrelated clock was captured. - Group only genuinely unrelated domains. Use
-asynchronouswhere there is no usable phase relationship. Use logical or physical exclusivity for mutually exclusive clocks, according to whether the exclusivity is a design-level selection or a physical limitation. - Include generated clocks where required. If the asynchronous intent covers a complete derived tree, include the generated clocks in the relevant group, using the syntax supported by the target tool.
- Review timing exceptions and CDC results. Confirm that expected cross-group paths are cut and that unrelated domains remain timed. Report names and diagnostics differ by tool and version, so use the reports available in the target flow rather than assuming one vendor’s output is universal.
- Retain CDC-specific requirements. Keep the synchronizers, protocol logic, and any required max-skew or net-delay constraints that make the crossing safe and implementable.
Why a cut path is not a safe crossing
Clock grouping changes what ordinary static timing analysis checks; it does not change the hardware behavior of a signal crossing into another clock domain. A crossing can still be vulnerable to metastability or to data being sampled inconsistently unless the design uses a suitable CDC architecture.
Intel’s Quartus Prime Pro Edition Design Recommendations (2022) says read and write domains in a dual-clock FIFO are typically constrained asynchronous with set_clock_groups. The same guidance separately calls for skew and net-delay constraints for Gray-coded pointer crossings. The example illustrates the division of responsibility: asynchronous grouping expresses the timing relationship, while the FIFO protocol, synchronizers, and crossing-specific constraints address the implementation.
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