FCRAM, or fast-cycle RAM, is a DRAM architecture described as a way to improve memory performance for communications equipment handling short, random accesses. Its central idea is that useful throughput depends on more than peak bandwidth: access latency, bank conflicts and bus turnaround can limit how quickly a system serves real traffic.
Why FCRAM was proposed
In a 2002 article, Kevin Kilbuck of Toshiba America Electronic Components framed FCRAM around networking workloads. Such systems may make short, unpredictable memory requests, so a high peak burst rate does not necessarily translate into high effective bandwidth. If requests repeatedly target a busy bank, or the bus spends cycles changing direction between reads and writes, the memory system can deliver less useful data than its headline bandwidth suggests.
Kilbuck wrote that “FCRAM was specifically designed to meet the requirements of communication designers.” The article presents FCRAM as a DRAM architecture co-developed by Toshiba and Fujitsu, not as a general claim that it is best for every memory workload. EE Times, March 19, 2002
How the architecture is described
The article describes FCRAM as combining pipelined row processing, a fast-access core, burst operation similar in broad outline to DDR, simplified commands and quicker bus turnaround. The cited design goal is to reduce delays that matter when requests are brief or arrive at different locations.
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Three-stage row pipelining
Row address decoding, memory-array access and transfer to the I/O buffer are treated as stages that can overlap. According to the article, a new row access can begin after the current row address has been latched in the decoder. This overlap is intended to keep work moving through the memory rather than waiting for every part of one access to finish before beginning the next.
Fast-access core
Kilbuck attributes the fast-access core primarily to smaller, segmented sub-arrays. The article reports random cycle times of 20–30 ns for FCRAM, compared with 60–70 ns for other DRAM types such as DDR. These are historical figures reported in the 2002 article, not current independent measurements or guarantees for a particular device. EDN republication of the article
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Commands and features
The historical description also distinguishes FCRAM’s interface and command set from conventional SDRAM/DDR implementations. Kilbuck says a function pin and additional address pins take the place of /RAS, /CAS and /WE; read and write commands include auto-precharge; power-down uses a /PD pin; write burst length is variable; and write CAS latency is one cycle shorter than read CAS latency. The article also says some functions, including burst stop and page mode, are omitted. These details describe the article’s account of the technology at that time; they are not a specification for a current part.
How to evaluate bandwidth beyond the peak number
Peak bandwidth assumes data can be transferred continuously under the relevant interface conditions. Effective bus bandwidth instead reflects how many cycles carry valid data compared with all cycles needed to complete requests. Latency, burst length, bank conflicts and the time required to reverse bus direction all affect that utilization.
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Kilbuck’s 2002 article models repeated accesses to the same bank and reports a bus-efficiency reduction of 37% for DDR versus 9% for FCRAM. Those are results from the article’s modeled comparison, which specifies assumptions about bursts, banks and clock frequencies; they are not universal performance figures. The article also notes that application randomness and system or CPU overhead affect actual system performance.
What to compare when choosing memory for a design
For a real system, match memory behavior to the workload and controller rather than choosing from peak bandwidth alone. These are the comparison points highlighted by the article:
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- Access pattern and burst length: Determine whether requests are long sequential transfers or short, scattered accesses.
- Initial access latency (tRAC) and row-cycle time (tRC): Consider both the delay to access data and the time needed to complete a row cycle.
- Same-bank access frequency: Repeated accesses to one bank can incur precharge or other timing penalties.
- Bus turnaround: Account for cycles lost when the bus changes between reading and writing.
- Peak bandwidth and effective utilization: Estimate how much of the bus’s theoretical capacity carries valid data for the workload.
- Controller and interface requirements: Confirm that the controller supports the specific device’s signaling, commands and timing. General historical discussion of DDR-like behavior does not prove compatibility with an arbitrary controller.
What the historical account does—and does not—establish
FCRAM is a useful case study in designing memory around access latency and utilization as well as transfer rate. The 2002 EE Times article documents how its author explained the architecture and its intended advantages. It does not establish present-day manufacturing, availability, support, or performance in a modern design. A current design decision would require up-to-date manufacturer documentation and evidence of compatibility with the intended controller.
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