An embedded bus or controller driver handles how data moves over a physical interface; a device-specific driver handles what the attached chip’s commands and responses mean. A subsystem API sits above the transport and gives applications and higher-level code a stable way to use UART, SPI, or I²C without depending on a particular controller. Keep those responsibilities separate, describe hardware relationships in the platform’s hardware description, and define transfer, concurrency, and error behavior before implementation.
What a bus driver does—and what it does not do
“Bus driver” can refer to the software that operates a bus controller or, more broadly, the layer that provides transport services to devices on a bus. In either use, its central responsibility is moving data reliably between software and hardware. It configures the controller, manages transfers, and reports transport-level outcomes. It should not absorb the attached chip’s functional protocol merely because that chip is the first one being supported.
| Layer | Primary responsibility | Typical concerns |
|---|---|---|
| I/O subsystem API | Expose stable operations to applications and higher-level drivers. | Operation names and data types, blocking rules, timeouts, errors, and concurrency expectations. |
| Bus or controller driver | Implement transport through a particular controller. | Register access, clocking, address or chip-select handling, transfer serialization, FIFO or DMA details, and interrupt delivery. |
| Device-specific driver | Implement the behavior of an attached chip using the bus services. | Chip protocol, register map, device timing, initialization, and functional behavior. |
For example, an SPI controller driver should know how to configure its controller and carry out an SPI transfer. A child driver for an SPI peripheral should know which commands, registers, and timing rules make that peripheral work. Keeping the boundary clear lets multiple devices share a controller and makes it less likely that application code will depend on controller-specific details.
Design the subsystem contract before the hardware implementation
Start with the interface that callers will use, not with a collection of register operations. Decide what a transfer means to its caller and document the contract so that controller implementations and device drivers agree on behavior.
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- Operations and data: specify the read, write, or transfer operations and the types and ownership of their buffers.
- Completion: state whether a call blocks, queues work, or completes asynchronously, and how a caller learns that it is finished.
- Timeouts and cancellation: define how long a caller may wait, what happens when the deadline expires, and whether an in-progress operation can be cancelled.
- Errors: distinguish failures of the transport from errors reported by a device protocol, and specify how each is returned.
- Concurrency: state whether callers may invoke operations concurrently, whether the API is reentrant, and what ordering guarantees apply.
In Zephyr, the generic UART, SPI, and I²C APIs provide subsystem-facing interfaces. Its documentation describes high-level calls through device-specific APIs such as i2c.h and spi.h as usually synchronous and blocking. Treat that as a platform convention to account for, not as a substitute for documenting the behavior of the particular operation and driver.
Represent hardware relationships in the hardware description
A devicetree is a hierarchical hardware description. Zephyr uses it to describe hardware to the Device Driver Model and to provide initial hardware configuration. Put board-level facts there rather than embedding them as unexplained constants in driver logic.
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- Identify the device with its compatible string and express its parent bus.
- Describe the bus address or chip-select as appropriate to that interface.
- Include interrupt, pin-control, clock, reset, GPIO, and power relationships required by the hardware.
- Validate mandatory properties during initialization and report a useful failure when configuration is missing or inconsistent.
The description expresses what is connected and how it is configured; it does not implement the controller’s transfer algorithm or the peripheral’s protocol. Keeping description and behavior separate supports a single, reviewable source of board hardware information and reduces board-specific assumptions in driver code.
Separate controller mechanics from child-device protocol
Implement the controller-facing operations independently from child-device behavior. The bus layer should own controller timing and transfer mechanics, serialize access to shared hardware, handle FIFO or DMA details where applicable, and surface transport failures. A child driver should request transfers through the appropriate subsystem interface and interpret the returned data according to its chip’s protocol.
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That separation also clarifies where a failure belongs. A controller timeout or bus-level NACK is a transport outcome; an unexpected value in a successfully read device register is a device-level outcome. Preserve enough information for the caller or diagnostic log to distinguish the two instead of collapsing every problem into a generic failure.
Choose polling, interrupts, or deferred work deliberately
Prefer interrupt-based operation when the peripheral supports interrupts. Zephyr’s Device Driver Model documentation says: “Each driver should support an interrupt-based implementation, rather than polling, unless the specific hardware does not provide any interrupt.” If the hardware has no usable interrupt, polling may be necessary; document that constraint rather than treating polling as the default design.
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Keep interrupt handlers short. They should acknowledge or capture the event and arrange for longer work to run in an appropriate deferred context. The design must preserve transfer ordering and ownership across that boundary: a buffer cannot be reused or released while deferred work still depends on it, and a later operation must not silently overtake an earlier one when ordering matters.
Define locking, ownership, and lifecycle rules
A shared controller needs a serialization policy so that concurrent clients cannot corrupt one another’s transfers or controller configuration. Decide whether serialization is internal to the bus driver or coordinated through a documented subsystem mechanism. Be explicit about which component owns transfer buffers, who may alter controller configuration, and whether nested calls are possible.
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Lifecycle behavior belongs in the design as well as the transfer path. Account for initialization order and the availability of clocks, resets, pins, and power dependencies. Define what happens when a device is suspended or resumed, when an operation is cancelled, and when a driver is removed or deinitialized on platforms that support those actions. A driver should not leave a shared controller in a state that surprises the next client.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How the design maps to Linux and Zephyr
Linux describes its driver model as a unification of earlier, disparate driver models and encourages other bus layers to follow the model established for PCI. The useful shared mental model for embedded systems is that a bus layer makes or represents a device, a matching mechanism selects a child driver, and that child uses subsystem-facing services while relying on the bus for transport. The exact discovery and lifecycle details depend on the operating system and bus.
| Design question | Linux perspective | Zephyr perspective |
|---|---|---|
| How is the driver model organized? | The kernel driver model unifies driver models; bus layers are encouraged to follow the model established for PCI. | The Device Driver Model provides a consistent model for configuring drivers, with generic type APIs including UART, SPI, and I²C. |
| How is hardware described? | Discovery or instantiation and matching depend on the bus and platform; avoid assuming one mechanism applies to every device. | Devicetree describes hardware relationships and supplies initial configuration to the Device Driver Model. |
| What should callers depend on? | Use the relevant subsystem-facing interface rather than reaching into controller-specific transport details. | Use the generic subsystem API for the relevant driver type rather than binding application code to a particular controller. |
| What transfer behavior should be expected? | Specify behavior for the chosen subsystem and operation; it is not uniform across all buses and drivers. | High-level calls through APIs such as i2c.h or spi.h are usually synchronous and blocking; document the contract callers actually receive. |
These are architectural comparisons, not claims that the two systems configure, enumerate, or execute every driver identically. For a specific implementation, follow the relevant subsystem’s documented matching, API, and lifecycle rules.
Validate the driver at three levels
A driver that compiles can still violate the bus contract, mishandle an error, or fail when integrated with the real peripheral. Test incrementally from the controller outward.
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- Controller behavior: verify register configuration, clocks, interrupt handling, and FIFO or DMA behavior on the target controller.
- Bus transactions: confirm the actual transaction sequence, addressing or chip-select behavior, timing, and ordering with suitable instrumentation such as transaction logs or a logic analyzer.
- End-to-end subsystem behavior: exercise the public API through the device driver and confirm both successful operations and how callers observe failures.
Include negative cases: NACK, timeout, framing error, overrun, arbitration loss where applicable, and device reset. Check not only the returned error but also whether the controller and shared bus recover to a usable state. Observability matters: transaction traces and logs should make it possible to identify whether a failure arose in the controller, the physical exchange, or the peripheral protocol.
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