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You can use C or C++ to describe an FPGA accelerator and run a separate program on a processor to prepare data, launch work, and collect results. The two parts are not interchangeable: high-level synthesis (HLS) converts a selected function into hardware, while the processor runs host software that communicates with that hardware through defined interfaces and memory arrangements. Ordinary CPU software does not automatically become efficient—or even fully synthesizable—FPGA hardware.
What “processor-compatible” means in an FPGA design
In a heterogeneous application, the processor and FPGA fabric perform different jobs. The processor runs the host application and runtime calls; the FPGA runs a synthesized kernel. AMD’s Vitis application-acceleration documentation describes host code running on an x86 or embedded processor and hardware kernels on an FPGA platform, with OpenCL or native XRT API calls managing runtime interaction.
Compatibility is therefore about the contract between the two sides, not a promise that the same C source runs unchanged on both. The host and kernel must agree on how work is started, how data is represented, and how inputs and outputs cross the hardware boundary. A host-attached accelerator card and an embedded system-on-chip can have different packaging, interfaces, and runtime requirements. Check the selected platform’s supported flow before designing around a particular API.
Choose a bounded function to synthesize
Start with a self-contained computation that has clear inputs, outputs, and storage bounds. Keep application tasks such as file access, user interaction, and general-purpose memory management on the processor unless the selected hardware flow specifically supports them in a kernel.
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For the Vitis C/C++ kernel flow, AMD’s UG1393 documentation says the kernel declaration must use extern "C" linkage. Treat that as flow-specific guidance: check the rules for your chosen release and packaging flow rather than assuming it applies to every HLS tool.
AMD also cautions that “Generally, off-the-shelf software cannot be efficiently converted into accelerated hardware on an FPGA.” Existing code may be a useful starting point, but it often needs to be rewritten to expose bounded storage, suitable parallelism, and predictable data movement. A function that compiles for a CPU is not necessarily synthesizable, and successful synthesis alone does not guarantee useful performance.
Sketch the host–kernel contract
Before optimizing, write down what the host provides and what the kernel returns. For example, a simple element-wise operation might accept an input array, an output array, and a count. This is an interface sketch, not a complete Vitis kernel or host program:
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extern "C" void transform(const int *input, int *output, unsigned count);The declaration alone does not specify how arrays are transferred, how the scalar is delivered, how memory is allocated, or how the kernel is launched. Those details belong to the selected platform and interface configuration.
Define interfaces and data layout explicitly
In Vitis HLS, the documented interface types include AXI4 memory-mapped master (m_axi), AXI4-Lite (s_axilite), and AXI4-Stream (axis). They serve different purposes: memory-mapped interfaces access memory, AXI4-Lite commonly carries control information, and streams carry sequences of data. The permitted argument forms differ by interface, so choose the interface architecture before finalizing kernel arguments.
- Memory-mapped arrays and pointers: define which side owns or provides the memory, the number of valid elements, and the access pattern.
- Scalar controls: specify values such as element counts or modes and how the host sets them.
- Streams: define the order and meaning of transfers, as well as how the producer and consumer coordinate.
Make the host’s data representation match the kernel’s. Structure field alignment, padding, array layout, and valid storage bounds all affect whether the hardware reads the intended values. Dynamic allocation common in C++ is often not synthesizable as hardware; determine storage requirements and express them in a form the selected flow supports.
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If an AXI protocol is used, AMD’s interface guidance also specifies a reset-polarity requirement. Consult the interface documentation for the selected release and design rather than assuming reset conventions are interchangeable.
Rewrite for parallel hardware and bounded resources
HLS infers a circuit from the C/C++ description together with constraints, defaults, and directives. The code is an input to hardware generation, not a direct specification of a CPU-like execution engine. Loops may be pipelined or unrolled; task-level parallelism and dataflow can be expressed; and arrays may become memories or registers after synthesis. Each choice can change resource use, timing, and throughput.
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- Set the required latency or throughput before changing the implementation.
- Identify storage sizes and data dependencies so the tool can build a bounded design.
- Review synthesis reports for resource use and scheduling, then check implementation timing.
- Change one relevant design choice at a time and compare the resulting reports.
Verify function before judging performance
A passing C simulation checks the software-level behavior of the testbench and function; it does not establish that generated RTL behaves identically or that the implemented design meets timing. AMD’s documented Vitis component workflow separates those checks:
- Run C simulation. Use representative inputs, boundary cases, and expected outputs to check the C/C++ function.
- Run C synthesis. Confirm the function can be synthesized and inspect inferred interfaces, scheduling, and resource estimates.
- Run C/RTL co-simulation. Compare the generated RTL behavior against the C testbench.
- Review implementation timing. Check timing reports for the implemented design; synthesis estimates alone do not demonstrate timing closure.
- Iterate. Adjust the kernel, interfaces, constraints, or memory arrangement, then repeat the checks relevant to the change.
Functional correctness and performance are separate outcomes. Do not claim speedup from a successful C simulation or from the presence of HLS directives; performance requires measurements on the intended platform under a defined workload.
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Data transfer can dominate a kernel’s total execution time. Global-memory latency and available bandwidth matter alongside the computation itself. AMD’s Vitis documentation describes bursts and coalescing as techniques that can help hide latency or improve bandwidth when the access pattern and directives support them; neither is an automatic benefit for every kernel.
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Separate memory ports can also matter when the platform and memory topology allow independent access. AMD’s 2019.2 Vitis Application Acceleration Development guide explains that mapping separate ports to different memory banks can enable parallel access. It also gives a 512-bit maximum global-memory transfer width for the example flow described in that guide. That figure is specific to the historical guide’s flow and example; do not treat it as a limit or recommendation for all current devices. Check the current target’s documentation and reports.
When comparing design approaches, consider the target and supported tools, whether the processor is an embedded hard processor or an external host, the interface and integration effort, memory layout and bandwidth, available resources and achievable timing, and how much useful parallel work offsets data-transfer overhead. There is no universal winner independent of the workload and platform.
Optional embedded prototyping example: Digilent Arty Z7
The Arty Z7 is one possible embedded prototyping board, not a universal recommendation for Vitis HLS. Digilent describes its Zynq-7000 system-on-chip as combining an Arm-based processor with FPGA logic and lists Arty Z7-10 and Arty Z7-20 variants. Its product information describes AMD Vivado and embedded C/C++ development support, but that alone does not establish support for a particular HLS/Vitis release or acceleration flow.
Before choosing the board, verify the exact variant, intended HLS and integration flow, supported software release, and local access to AMD software. Digilent specifically advises checking software availability by country.
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