At DAC 61 in 2024, the conversation about electronic design automation (EDA) widened beyond designing an individual chip. Nitin Dahad’s conference account described a “chips to systems” focus: as designs bring together chiplets, interconnects, software, packaging and system requirements, engineering decisions increasingly need to account for how the pieces work together. The account captures conference themes and discussions—not a comparative test of EDA tools or proof that a particular approach solves the problem.
Why EDA is being discussed at the system level
EDA tools support the design and verification of electronic systems, including integrated circuits. The challenge described at DAC 61 is that a design’s important constraints do not stop at the boundary of one chip. A chiplet-based package, for example, depends on connections among multiple dies as well as the surrounding system. Choices made at one level can affect integration and the behavior expected at another.
Dahad’s report connects that growing complexity with a need for broader system context. It presents this as a synthesis of conference conversations, not a measured technical result. The practical shift is in scope: chip design remains central, but it is discussed alongside system architecture and integration rather than in isolation.
What DAC 61 put in that wider frame
Chiplets and interconnects
Chiplets and the links between them featured in the report’s account of system complexity. Breaking a design across dies makes integration and interconnect decisions part of the overall design problem. The article does not quantify the resulting engineering costs or compare particular chiplet methods.
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AI and autonomous systems
Artificial intelligence and autonomous systems were among the broader topics Dahad associated with the “chips to systems” framing. Their presence signals that EDA discussions were situated within applications and systems with demands beyond an individual component; the report does not claim that one EDA workflow addresses all those demands.
Security and design tradeoffs
A microelectronics security panel discussed regulation and the cost and schedule tradeoffs involved in secure design. The report offers no figures for those tradeoffs, but it highlights a practical tension: security requirements must be considered alongside engineering effort and delivery schedules.
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Approaches discussed—and what the report establishes
The conference account points to several ways people were thinking about the problem. They differ in scope and method, but the report does not evaluate them against one another.
| Approach or theme | Problem it relates to | Evidence in the report |
|---|---|---|
| AI applied to EDA | Using generative AI in design workflows | Emerging area; Dahad names startups Silimate and PrimisAI that he encountered. The account does not establish their current availability or product capabilities. |
| Wafer-level digital twins | Connecting design and manufacturing insight | Silvaco CEO Babak Taheri discussed the concept, according to Dahad’s report. |
| Fab technology co-optimization (FTCO) | Considering fabrication technology alongside design | A term attributed to Taheri in the report; the available account does not establish it as a broadly adopted standard term. |
| Security-focused design | Addressing security requirements while managing cost and schedule | A conference panel topic, as reported by Dahad; no quantified comparison or outcome is given. |
These are reported conference discussions, not evidence that a particular tool or method has resolved system complexity. They also span different kinds of evidence: conference observations, discussion of concepts and named startups, rather than product tests or measured results.
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How to interpret DAC 61’s submission figures
Dahad wrote that he was told DAC 61 received about 1,500 technical paper and presentation submissions, with research paper submissions up 34%. The article does not identify the source of those figures or provide the underlying baseline for the percentage, so they should be treated as secondhand figures reported by the author rather than independently verified official counts. They should not be combined with figures from the next year’s conference.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What later DAC 2025 material adds
DAC 2025 provides follow-up context for the continuing breadth of EDA discussions, not additional evidence about what happened at DAC 61. The official 2025 Call for Contributions frames EDA as spanning chips and systems, including mechanical and electromagnetic interactions. It identifies lower power, higher reliability and more agile systems as challenges, and lists multi-die systems, 3-D integration, heterogeneous architectures and security among its topics. This describes the conference’s scope; it does not show that those challenges have been solved.
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DAC’s April 2025 preview reported 1,862 final research submissions, a 20.3% year-over-year increase, and 370 Engineering Track submissions. Its July 2025 post-event announcement said AI-related sessions accounted for 32% of the technical program, an 80% year-over-year increase, and reported 6,012 preliminary attendee registrations. These are DAC 2025 figures, not DAC 61 statistics. The post-event announcement also quotes DAC 2025 General Chair Helen Li describing AI as an engine for electronic design; that is her characterization, not a neutral measurement of the field.
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