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There is no single best memory for every FPGA. Choose by working-set size and access pattern first, then check the exact device and board’s supported interfaces, achievable bandwidth, latency, power, and implementation effort. On-chip RAM, HBM, DDR or LPDDR, and host memory serve different roles; an interface’s advertised peak does not guarantee that an application will reach it.
Start with the workload, not the memory label
Before comparing HBM with DDR, determine whether the design is memory-bound. Extra theoretical bandwidth will not accelerate a workload bottlenecked by compute, host transfers, serialized requests, or too little independent work in flight.
Characterize the workload and the platform together. Record:
- Working-set size, including buffers and metadata, and how much data can be reused.
- Whether accesses are sequential, regular, random, or scattered, and how many independent streams run at once.
- The read/write mix, latency deadline, and required concurrency.
- The exact FPGA, board, memory controller and IP, toolchain version, and supported memory configuration.
These details determine whether capacity, latency, or parallel bandwidth is the real constraint—and whether the platform can support a proposed memory at all.
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Match the workload to a memory tier
On-chip block RAM, UltraRAM, and other local RAM
Use on-chip RAM for small working sets close to the logic: buffers, FIFOs, lookup structures, and reusable tiles. Local storage can avoid repeated trips to external memory, but its capacity is limited by the FPGA’s resources. AMD Vitis guidance says distributed RAM is not suited to large memories and, in its design context, recommends block RAM or UltraRAM for structures larger than about 128 bits. That guidance is context-specific, not a universal device threshold.
In-package HBM
HBM stacks are integrated into selected FPGA or adaptive SoC packages. They can offer high aggregate bandwidth and avoid some external-memory board routing, but benefit depends on the design distributing requests across the available channels or pseudo-channels and issuing enough independent work. Check the exact device’s capacity and organization as well as its supported controller and software/IP path.
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External DDR and LPDDR
External memory can provide capacity and interface options suited to larger working sets. The actual configuration depends on the FPGA family and board. Confirm the memory generation and data rate, component or DIMM form factor, ranks, capacity, controller support, and board routing in the target platform’s documentation. A generic PC DIMM is not automatically compatible with an FPGA card.
Host memory over PCIe, CXL, or another fabric
Host-attached memory may suit capacity or sharing requirements, but compare the full path: link bandwidth, latency, coherency behavior, and software overhead all affect usable performance. Intel describes PCIe 5.0 and CXL options for Agilex 7 M-Series; actual support depends on the device and platform configuration.
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Compare the constraints that shape the choice
| Factor | Question to answer |
|---|---|
| Capacity | Will usable memory hold the working set, buffers, and metadata? |
| Sustained bandwidth | What can this access pattern achieve, rather than what is the interface peak? |
| Latency | What is end-to-end read or write latency after controller, interconnect, and queueing effects? |
| Parallelism | How many independent ports, banks, channels, or pseudo-channels can operate concurrently? |
| Power and thermal limits | What does the complete memory subsystem consume under the expected traffic mix? |
| Board and package | Does the option require external routing, DIMM slots, or a particular integrated package? |
| Compatibility | Does the exact FPGA, board, controller IP, tool version, and memory component support the configuration? |
| Engineering effort | What partitioning, RTL or HLS changes, drivers, constraints, and verification are required? |
| Total cost | What are the device or board, memory, power, cooling, and engineering costs together? |
Compare bandwidth figures only when the device, configuration, and measurement basis align. A capacity that barely fits the data may also leave too little room for buffers and metadata; account for those when evaluating whether a tier is large enough.
What published FPGA memory figures do—and do not—tell you
The figures below are vendor specifications or comparisons, not independent application benchmarks. Product-level “up to” values do not establish the throughput a particular design will deliver.
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| Platform or statement | Published figure | Qualification |
|---|---|---|
| Intel Agilex 7 M-Series, current product page | Up to 1 TB/s; up to 32 GB HBM2E; DDR5/LPDDR5 controller support up to 5,600 Mbps | Family-level vendor specifications; verify the target part’s datasheet and configuration. |
| Intel Agilex 7 M-Series, FPGA memory-solutions FAQ | 410 GB/s per HBM2e stack; up to 16 GB per stack | Vendor FAQ figures; confirm the exact device and stack configuration. |
| Intel Agilex 7 M-Series historical comparison | 1.099 TB/s theoretical maximum | Intel’s comparison footnote dated October 14, 2021 specifies two HBM2e banks using ECC as data plus eight DDR5 DIMMs. Its comparisons with AMD Versal HBM and Achronix reflect figures stated at that time, not a current industry ranking. |
| AMD Virtex UltraScale+ HBM family | Up to 460 GB/s; up to 16 GB HBM2 | Vendor family-page maximums; listed model capacities range from 4 GB to 16 GB. |
| AMD Versal HBM Series | Up to 819 GB/s; 32 GB HBM2e | Vendor product-page maximums. AMD’s “up to 6X” bandwidth and “65% lower power per bit” comparisons are versus a Versal Premium VP1502 with four LPDDR4-4266 components, based on AMD internal analysis in May 2023. |
| AMD Alveo accelerator cards in Vitis guide UG1700 version 2026.1 | 16 GB HBM on U55C; 8 GB on U280 and U50 | AMD’s guide, released June 23, 2026, describes two HBM stacks in the FPGA package and says multiple AXI masters are needed to get better-than-DDR performance in the implementation it describes. |
The interface and design details behind a vendor maximum matter as much as the headline. In particular, do not compare a theoretical platform aggregate with a measured application result or treat a vendor comparison from a specific date as an up-to-date ranking.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to realize more of the available bandwidth
Bandwidth depends on both memory organization and how the design issues requests. AMD’s Vitis HLS guidance recommends concurrent ports where possible and warns that accesses to the same bank serialize. It also says: “Transferring data in bursts hides the memory access latency and improves bandwidth usage and efficiency of the memory controller.” This is implementation guidance from AMD’s Best Practices for Designing with M_AXI Interfaces (2024.1), not a guarantee of a particular measured result.
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- Map independent traffic to separate banks or channels. Partition arrays or buffers when simultaneous access is needed; avoid unintentionally routing multiple active users through one bottleneck port.
- Use long legal bursts for regular transfers. AMD gives a 512-bit AXI port with a burst length of 64 elements as an example representing 4 KiB. It is an example for that port width, not a universal burst setting. Check the interface and controller limits for the target design.
- Keep enough requests in flight to cover latency. Multiple outstanding requests can help hide latency, but use BRAM or URAM resources. Choose the amount based on the design’s resource budget and measured behavior.
- Check the complete access path and timing. Intel’s HBM guidance notes that read latency includes the command path, memory read latency, and the return path through the controller. Timing closure in the user logic also affects realized throughput.
- Profile on the actual design. Record the workload, read/write pattern, memory placement, number of ports, tool and IP versions, clock rate, and whether the result is theoretical, simulated, or measured on hardware.
Make the platform-specific decision
- Estimate the real footprint. Include data that must be resident simultaneously plus buffering and metadata; identify what can instead be reused from local RAM.
- Eliminate incompatible options. Use the exact board manual and device documentation to check supported memory types, capacity, component or DIMM format, controller, and tool/IP support.
- Test the access pattern, not just the peak. Estimate or measure sustained throughput and end-to-end latency for the workload’s concurrency, burst pattern, and read/write mix.
- Account for implementation and system cost. Include resource use, power and cooling, board or package constraints, and the engineering work needed to expose parallelism.
- Validate the candidate configuration. Benchmark or profile the design on the target platform, then revise bank mapping, ports, bursts, or outstanding requests if memory is the bottleneck.
The resulting choice may be a hierarchy rather than a single memory: keep reusable, latency-sensitive data close to the logic and place larger working sets in a supported external or in-package tier. The proportions and interfaces must follow the workload and exact platform, not a generic FPGA-versus-memory rule.
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