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The original Raspberry Pi RP2350 security challenge is closed. A later challenge targets a different weakness—power side-channel attacks against the chip’s AES implementation—and its published deadline is still in the future as of 3 October 2026.
What did the original RP2350 challenge ask people to break?
It was a hardware-security challenge, not a general invitation to compromise Raspberry Pi devices. The target was a 128-bit secret programmed into the RP2350’s one-time-programmable (OTP) memory at row 0xc08. Participants had to recover it after the chip was configured in its standard secure mode.
What “secure mode” meant
The official challenge repository specified a setup that enabled secure boot, disabled debug access, and wrote and locked the OTP data. Enabling security permanently disables the RP2350’s two Hazard3 RISC-V cores, while its Arm Cortex-M33 cores remain operable. The challenge was therefore to defeat protections in the configured chip, not simply read an unprotected memory value.
The 128-bit value was the challenge’s secret; it was not a published password or a value readers could retrieve from the challenge description. Raspberry Pi presented the exercise as a way to test the chip’s security features before broad deployment and to publish weaknesses openly.
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- The Raspberry Pi Pico is a beginner-friendly microcontroller board that uses MicroPython to give you a taste of the Internet of Things and microcontrollers. The RP2040 is a well-designed microprocessor that can be utilized in almost any Internet of Things project. It has enough power to complete the task quickly.
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What happened to the $10,000 offer?
| Challenge | Target and approach | Prize and timing | Status |
|---|---|---|---|
| Original RP2350 challenge | Recover the locked OTP secret from a chip in secure mode. Raspberry Pi later reported that all valid winning approaches required physical access, with varying degrees of intrusiveness. | Raspberry Pi announced a $10,000 prize at DEF CON 32 in August 2024. It extended the deadline to midnight UK time on 31 December 2024 and doubled the prize to $20,000. | Closed. On 14 January 2025, Raspberry Pi reported four valid submissions. |
| Follow-on AES challenge | Develop a practical power side-channel attack against the power-hardened AES library used by the decrypting bootloader. | Announced in July 2025 with a $20,000 prize. The challenge repository lists 31 October 2026 as the end date. | As of 3 October 2026, the listed deadline is still in the future. Check the official challenge repository for current rules and status before attempting to enter. |
The original offer was open to anyone, not only people attending DEF CON. Its closure means the original $10,000 bounty is not available for new entries; the later $20,000 figure applied to the extended first challenge, not a currently open version of that same contest.
How is the AES challenge different?
The follow-on contest changes both the security target and the kind of evidence an attacker must collect. The first challenge concerned recovery of data from OTP after secure boot and debug protections were configured. The second concerns whether power consumption during AES operations leaks enough information to mount a practical correlation attack.
Rank #2
- RPi Pico 2 W Microcontroller Board (pre-soldered header (color-coded)), Based on Official RP2350 Chip, Dual-core & Dual-architecture Design. Upgraded hardware from Pico 2 with wireless communication, onboard antenna, features 2.4GHz 802.11n WIFI and Bluetooth 5.2.
- Adopts unique dual-core and dual-architecture design: dual-core Arm Cortex-M33 processor and dual-core Hazard3 RISC-V processor, flexible clock running up to 150 MHz.
- Onboard Infineon CYW43439 wireless chip, supports WIFI 4 wireless and Bluetooth 5.2.
- 520KB of SRAM, and 4MB of on-board Flash memory.
- Castellated module allows soldering direct to carrier boards. USB 1.1 with device and host support. Low-power sleep and dormant modes. Drag-and-drop programming using mass storage over USB.
| Comparison | Original OTP challenge | Follow-on AES challenge |
|---|---|---|
| Target | 128-bit OTP secret in row 0xc08, protected by the challenge’s secure configuration. |
AES implementation in the decrypting bootloader. |
| Attack focus | Recover the secret despite secure boot, disabled debug, and locked OTP. Raspberry Pi says every valid submission used physical access; it does not characterize all winning approaches as a single technique. | Practical power side-channel analysis, using correlation against AES activity. |
| Countermeasures or design details | Secure configuration disables the Hazard3 RISC-V cores while leaving the Arm M33 cores available. | The announced AES implementation uses multi-way secret sharing and randomizes operation and data order. In February 2026, organizers removed memory-access randomization to make correlation attacks more tractable. |
| Hardware burden | The official setup uses an RP2350 board, such as a Raspberry Pi Pico 2, in BOOTSEL mode with the supplied challenge firmware. Raspberry Pi also described a Hextree RP2350 Security Playground board that exposes voltage rails and clock input and provides a GUI for glitching experiments. | The challenge is based on power measurements, but the announcement and repository details cited here do not establish a single required instrument list or minimum equipment configuration. |
| Revision or implementation status | Raspberry Pi says challenge findings included boot-ROM vulnerabilities later addressed in the A4 stepping. | The cited challenge information describes changes to the AES implementation’s randomization; it does not specify a silicon stepping requirement. |
| Prize, deadline, and status | Originally $10,000; extended to $20,000 with a 31 December 2024 deadline. Closed with four valid submissions reported in January 2025. | $20,000; repository lists 31 October 2026. The deadline and status can change, so confirm the repository before participating. |
What hardware do you need to try the setup?
For the original challenge firmware
The official setup uses an RP2350 board in BOOTSEL mode to load the supplied challenge firmware. A Raspberry Pi Pico 2 is the most direct board option described for reproducing that setup. This does not reopen the contest or create a route to submit to the concluded OTP challenge.
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For voltage- or clock-glitching experiments
Raspberry Pi described the Hextree RP2350 Security Playground as a board built to expose the RP2350’s voltage rails and clock input, with a GUI for glitching experiments. That makes it a purpose-built platform for physical fault-injection work; the cited material does not establish that it is mandatory for either contest.
Rank #3
- Latest Version: Higher core clock speed, double memory, more powerful Arm cores, optional RISC-V cores (compared to the 1 series) (This W version has onboard wireless LAN and Bluetooth)
- Switchable Cores: Allows users to choose between dual industry-standard Arm Cortex-M33 cores and dual open-hardware Hazard3 cores
- Compatibility: Delivers a significant performance boost, while retaining software- and hardware-compatible with the 1 series
- Detailed Tutorial: Provides step-by-step guide with MicroPython, C and Processing (Java) Code (The download link can be found on the product box) (No paper tutorial)
- Example Projects: Each project has schematics, wiring diagrams, complete code and detailed explanations (Need extra items)
For the AES side-channel challenge
Because the target is power consumption during AES operations, the relevant method is power side-channel measurement and correlation rather than simply loading the original OTP challenge firmware. The published material cited here does not prescribe a complete equipment bill of materials, so do not assume a particular oscilloscope, probe, or acquisition setup is an official entry requirement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How can you enter the current challenge?
The original OTP contest is closed, so there is no current entry procedure for its $10,000 offer. For the AES challenge, use the official Raspberry Pi challenge-2 repository as the authority for eligibility, submission format, deadline changes, and any setup instructions. Its listed end date is 31 October 2026; that is a repository deadline, not a guarantee that entries remain open or that the rules have not changed since publication.
Rank #4
- RPi Pico 2 microcontroller board (with yellow Pre-Soldered Header) is powered by Official RP2350 microcontroller chip, with unique dual-core and dual-architecture design, running up to 150 MHz, embedded 520KB of SRAM and 4MB of on-board Flash memory, as well as 26x multi-function GPIO pins
- Adopts unique dual-core and dual-architecture design: dual-core Arm Cortex-M33 processor and dual-core Hazard3 RISC-V processor, flexible clock running up to 150 MHz
- 520KB of SRAM, and 4MB of on-board Flash memory
- 26 × multi-function GPIO pins. 2 × SPI, 2 × I2C, 2 × UART, 3 × 12-bit ADC, 24 × controllable PWM channels
- Castellated module allows soldering direct to carrier boards. USB 1.1 with device and host support. Low-power sleep and dormant modes.
For broader technical context, Raspberry Pi’s RP2350 product portal links the current datasheet and the whitepaper “Understanding RP2350’s security features.” These references help explain the chip’s security architecture, but the contest repository governs challenge-specific instructions.
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Quick Recap
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- Compatible models: Raspberry Pi Pico / Pico H / Pico W / Pico WH / Pico 2 / Pico 2 W (NOT included in this kit)
- GPIO status LED: LED on if GPIO outputs / inputs high level, LED off if GPIO outputs / inputs low level
- Independent LED: The status LED is driven by the chip instead of the GPIO so the GPIO will not be affected
- Terminal block and header: Connect to all pins of the main board, 2.54 mm (0.1 inch) pitch
- Pin name: The name of each pin is printed next to it
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