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CPU cache and direct memory access (DMA) are not competing ways to do the same job. Cache speeds CPU access to recently used data; DMA lets a device transfer data to or from memory without the CPU copying each byte. They can be used together. For programmers, the key trade-off is whether the device and CPU can share a buffer correctly and whether setup, synchronization, and any fallback copying outweigh the benefit for the workload.
What cache and DMA each do
CPU cache keeps data close to the processor
A CPU cache holds copies of memory data the processor has accessed, so later loads or stores can be served close to the CPU when the access pattern has locality. Its benefit depends on reuse, access pattern, and cache capacity. Cache is part of CPU memory access; it does not itself transfer data to a device.
DMA lets a device move data to or from memory
With DMA, a device can read from or write to memory without the CPU copying every byte in the transfer. This can leave CPU time available for other work, but it does not eliminate driver work: software still arranges device-visible memory, configures transfers, observes completion, and follows the required synchronization and ownership rules.
Where the trade-offs arise
| Choice or condition | Potential benefit | Cost or risk |
|---|---|---|
| CPU repeatedly accesses data with locality | Cache may serve recent data close to the processor. | Capacity and access patterns affect hits; a device doing DMA may not automatically participate in CPU-cache coherence. |
| Device transfers a large or sustained stream directly with DMA | The CPU avoids copying every byte and can do other work. | Mapping, descriptors, completion handling, synchronization, and device address constraints still require attention. |
| Coherent DMA allocation for shared control data | CPU and device can observe each other’s writes without explicit cache-flushing primitives. | Linux warns that coherent memory can be expensive on some platforms and may be allocated at page granularity; consolidate small requests or consider DMA pools for suitable small allocations. |
| Streaming DMA mapping for transfer buffers | Supports explicit ownership transitions between CPU and device. | Synchronization may flush or invalidate CPU caches and can take time, particularly for large buffers. |
| Bounce buffering | Can make a transfer possible when direct device access is constrained. | Copies between the original and staging buffer consume CPU resources and can make the transfer slower than direct DMA. |
| A shared DMA buffer used across subsystems | Provides a framework for sharing and coordinating access instead of treating each device’s buffer as isolated. | Attachment, mapping, lifetime, CPU access, and asynchronous completion still need correct handling. |
There is no universal buffer-size threshold at which DMA becomes faster than CPU copying. The crossover depends on the device, interconnect, CPU, transfer setup, mapping lifetime, cache behavior, and access pattern; measure the actual workload and platform.
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How Linux handles DMA memory
The details below describe Linux driver APIs; they are not universal rules for every operating system, kernel version, architecture, or device. Follow the DMA API documentation for the target kernel and device.
Coherent allocations simplify visibility, not every ordering issue
Linux describes coherent memory as memory where a write by the processor or device can immediately be read by the other without worrying about caching effects. Coherent allocations can be costly on some platforms, so the kernel documentation recommends consolidating small requests or using DMA pools for suitable small, descriptor-like allocations. Visibility also does not remove all ordering concerns: processor write buffers may need flushing before the driver tells a device to read the memory. See the Linux DMA API HOWTO.
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Streaming mappings require ownership transitions
For streaming mappings, the driver must follow the mapping direction and synchronize when ownership moves between CPU and device. Linux explains that moving a buffer from the CPU domain to the device domain synchronizes CPU caches for the region, usually by flushing or invalidating them; this can take time, especially for large buffers. See Linux DMA attributes.
The versioned Linux v5.17 DMA API page specifies the following direction rules:
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DMA_TO_DEVICE: synchronize after the software’s last modification and before handing the buffer to the device.DMA_FROM_DEVICE: synchronize before the driver accesses data the device may have changed.- Bidirectional mappings: synchronize before handoff and before subsequent CPU access.
That v5.17 page also says mapped regions must begin and end on cache-line boundaries, and recommends page boundaries if cache-line width cannot be determined at runtime. These are versioned API details; check the documentation for the kernel you target.
Coherency, ordering, and correctness
Cache coherency and memory ordering are related concerns, but one does not substitute for the other. Linux warns that not all systems maintain cache coherency with respect to DMA-capable devices. On an incoherent system, a device may read stale RAM while newer dirty data remains in CPU cache, or device writes may be hidden or overwritten by CPU cache lines. The kernel’s appropriate DMA and cache-management paths must handle these cases. See the Linux memory-barrier documentation.
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A memory barrier is not a universal cache-maintenance operation. Linux documents DMA-specific barrier primitives for ordering reads and writes to consistent memory shared with DMA-capable devices. Use the mapping, synchronization, and ordering rules appropriate to the memory type and device protocol; do not assume that a barrier alone makes incoherent DMA safe.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.DMA addresses and bounce buffers
A DMA address is for the device, not a CPU pointer. Linux’s dma_addr_t may be translated relative to CPU physical and virtual addresses, and the CPU cannot dereference it as an ordinary pointer. The device’s DMA mask and addressable memory range must also be respected; use the Linux DMA API rather than passing a CPU pointer to hardware as if it were necessarily a DMA address. See the Linux DMA API HOWTO.
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When a device cannot directly reach a target buffer, or another constraint requires staging, Linux can use SWIOTLB bounce buffering. The CPU copies between the original buffer and the bounce buffer, so this is slower and more CPU-intensive than direct DMA. Linux documents its use for addressing limitations and certain confidential-computing and IOMMU-granule scenarios in the SWIOTLB documentation.
Sharing buffers across Linux subsystems
When a buffer passes between devices or subsystems, Linux dma-buf provides a framework for sharing it and coordinating asynchronous hardware access. The associated dma-fence and dma-resv mechanisms represent asynchronous completion and manage reservations and fences for ordered access. They do not remove the need to handle attachment, mapping, lifetime, CPU access, or synchronization correctly. See the Linux dma-buf documentation.
Quick Recap
A practical way to choose
- For CPU-heavy work with repeated, local access: focus on the CPU’s access pattern and cache behavior; DMA does not improve CPU loads merely by existing.
- For device transfers: consider DMA to avoid CPU copying, then account for mapping lifetime, synchronization frequency, completion handling, and device addressability.
- For data shared by CPU and device: choose the appropriate coherent or streaming approach and follow its visibility, ownership, and ordering rules.
- For constrained devices or memory: account for the possibility of bounce buffering and its extra copies.
- For performance decisions: measure the actual access pattern and platform rather than relying on a generic byte threshold.
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