Cache can make an SoC’s CPU spend less time waiting for data, but adding capacity is not a guaranteed speed boost. The practical route is to identify a memory bottleneck in a representative workload, measure cache behavior on the target SoC, make a focused change, and test the result.
How cache can speed up an SoC CPU
A cache is a small, fast store that keeps copies of data the processor may need again. When requested data is available at the cache level being checked, the CPU can avoid fetching it from a slower level of the memory hierarchy. If it is absent, the request must be served from another cache or memory; the cost depends on the particular processor, hierarchy and workload.
Cache is part of a processor’s microarchitecture, not a feature that behaves identically across all CPUs. Arm distinguishes the architectural contract—the instruction set and related software-visible behavior—from microarchitecture choices such as cache levels. Its architecture is used in more than 350 billion shipped chips across markets, an indication of reach rather than a cache-performance statistic. Arm’s architecture overview
Cache levels and organization vary
Many processors use levels labeled L1, L2 and sometimes L3, but those labels do not guarantee the same capacity, latency, sharing or inclusion policy. A level may be private to a core or shared among several cores. Some designs keep copies of data found in one cache level in another (inclusive); others do not (non-inclusive). These choices affect access time, data movement and coherence traffic between cores.
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For software developers, the important point is not to assume a cache layout from the label. Consult the documentation for the exact SoC and core, and treat cache capacity as one part of a system that also includes interconnects, memory, power limits and the operating system.
Measure cache behavior before changing anything
Start with the workload that matters: a repeatable application or task running under representative conditions on the target SoC. Record a baseline for the outcome you want to improve—such as latency or throughput—and, where relevant, power consumption. Then use a profiler or platform-supported performance monitoring unit (PMU) events to find whether cache refills or misses are associated with the code that consumes meaningful time.
- Make the workload reproducible. Fix the input, configuration and run conditions as far as practical; record the SoC, core, operating system and compiler settings.
- Capture a baseline. Measure the actual application outcome before tuning. A cache counter alone does not show whether users will see a benefit.
- Sample supported cache events. Use the platform’s profiler or PMU to examine cache misses, refills or data accesses where those events are available. Event names and availability differ across processors and cache controllers, and profiler permissions may depend on the platform.
- Find the responsible code. Attribute samples to functions or source locations. Check whether the hot code is waiting on data, rather than assuming every slow function is cache-bound.
- Inspect access patterns and sharing. Look at working-set size, traversal order, data layout and whether cores are passing or updating shared data.
- Change one factor and repeat. Re-run the same workload and compare latency or throughput, counters and power where relevant. Keep a change only if the measured result improves the target outcome.
Arm’s profiling guidance demonstrates this kind of investigation using hardware counters and hotspot analysis. In its example, L2 data-cache misses point toward column-wise traversal of a two-dimensional array as a likely cause. That diagnosis is an illustration, not a claim that every array or processor behaves the same way. Arm performance-analysis guidance
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Use locality to reduce unnecessary cache pressure
Programs often benefit when they access data close together in time or memory: reusing recently accessed values is temporal locality, while processing nearby addresses is spatial locality. A data layout or traversal that matches the program’s use can reduce avoidable movement through the hierarchy. But cache-aware changes can also add complexity, and their value depends on the actual core, compiler and workload.
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For a row-major array, adjacent elements in a row are stored next to one another. Traversing across a row therefore tends to access nearby addresses; traversing down a column may jump between distant locations. Arm’s example uses column-wise traversal as a possible explanation for L2 data-cache misses. If profiling points to a similar pattern in your code, compare traversal orders on the target system rather than assuming a universal speedup.
Other candidates to investigate include the size of the active working set, repeated access to shared data, and code paths that touch more data than the task needs. Arm’s Streamline guidance describes data-access and refill counters, while noting in practice that available cache events depend on the platform. Arm Streamline user guide
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Hardware cache choices are trade-offs, not a “bigger is faster” rule
For SoC architects, cache decisions should be evaluated against the expected workload and the entire design budget. More capacity can help when a working set would otherwise miss frequently, but cache also takes area and power, and may affect access latency and data movement. A shared cache can serve multiple cores, yet access and coherence traffic may change under contention. There is no single capacity or arrangement that is best for every workload.
- Capacity and latency: assess each level against likely working sets and access frequency.
- Private or shared: consider per-core access, contention and how data is shared.
- Inclusion policy: evaluate how inclusive or non-inclusive organization affects effective capacity and traffic.
- Interconnect and coherence: account for the cost of moving or coordinating data across cores.
- Area and power: weigh cache resources against the rest of the SoC and its operating envelope.
- Measured workload results: validate performance on representative tasks, not only theoretical capacity.
Intel’s overview illustrates how these choices can shift between processor generations. It describes a prior design with a 256 KB-per-core mid-level cache and a 2.5 MB-per-core shared inclusive last-level cache, compared with the discussed Xeon Scalable family’s 1 MB-per-core mid-level cache and 1.375 MB-per-core shared non-inclusive last-level cache. Those figures describe the named designs, not all Intel processors or a universal performance ranking. Intel also notes that effective behavior can differ between single-threaded and shared multithreaded workloads, so tuning may need to be workload-specific. Intel’s cache-hierarchy overview
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Intel’s separate support table lists other capacities for specified third-, fourth- and fifth-generation Xeon Scalable configurations. Check the exact generation and configuration before applying a figure to a particular system. Intel Xeon cache-size support table
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Different SoCs solve cache sharing in different ways
Recent vendor designs illustrate that cache hierarchy is an implementation choice, not a fixed recipe. Qualcomm announced Flex Cache in August 2026 as a dynamically allocated shared cache pool for heterogeneous cores. Its announcement says: “Qualcomm Oryon Flex Cache allows heterogeneous cores to access the same cache pool, with cache dynamically allocated based on workload.” Qualcomm also described Oryon as the first mobile CPU to reach 5 GHz; these are vendor claims, not independent comparative evidence, and commercial product specifications should be checked for a specific device. Qualcomm’s August 2026 announcement
AMD’s Zen 4 materials describe generational changes to cache and the load/store hierarchy, and report up to a 13% IPC increase for its stated comparison. That figure is AMD’s claim for that comparison, not an independent benchmark of cache tuning or a promise for another workload. AMD’s Zen 4 announcement
These descriptions are examples of distinct design approaches, not a head-to-head test. A number or feature from one vendor cannot establish which SoC will be faster for a particular application.
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Can you upgrade cache in a finished SoC?
Cache hierarchy is built into the processor’s microarchitecture. The evidence here does not establish a physical cache-upgrade product for a finished SoC. If a device’s CPU is cache-limited, practical options are generally to improve software access patterns where profiling supports it, adjust system or workload configuration where available, or choose a different processor design for a future product—not to assume that more cache can be installed after manufacture.
How to decide whether a cache optimization worked
A lower miss count is not automatically a faster application, and a faster run in one test is not proof of a repeatable gain. Compare the same representative workload before and after the change on the target SoC; report only measured results, with the conditions that produced them. Results can vary with the SoC, core, operating system, compiler, thermal and power envelope, and application.
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