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Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Broadcom announced on November 6, 2000 that it had signed a definitive agreement to acquire SiByte, a Santa Clara fabless semiconductor company developing highly integrated processors for networking and communications. The transaction was designed to add SiByte’s 64-bit MIPS technology to Broadcom’s switches, communications DSPs, security products and physical-layer devices. Broadcom expected the deal to close within 60 days, subject to shareholder, regulatory and other customary conditions; the sources available for this history do not establish the exact legal closing date.
Why Broadcom bought SiByte
SiByte gave Broadcom a processor platform aimed at the rapidly expanding broadband and Internet-infrastructure equipment market. Broadcom already supplied networking and communications components, while SiByte was developing high-performance system processors that could run networking workloads directly.
Broadcom said the combination would pair SiByte processors with its IP switches, communications DSPs, security products and physical-layer devices. That breadth was intended to help equipment makers build more complete systems for broadband access, optical networking, wireless communications and other carrier and enterprise applications.
SiByte also brought commercial traction rather than only a laboratory design. Broadcom said SiByte had multiple design wins and firm, multi-year contracts totaling more than 1.3 million units, with average selling prices in the multi-hundred-dollar range. SiByte chief executive Dan Dobberpuhl said Broadcom’s product breadth and geographic reach could expand SiByte’s broadband-processor business worldwide.
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What Broadcom agreed to pay
The announced consideration was entirely in Broadcom Class A shares and could reach 9.3 million shares:
| Component | Shares | Condition |
|---|---|---|
| At closing | About 5.6 million | Issued when the transaction closed, subject to the agreement’s conditions |
| Additional consideration | About 3.7 million | Tied to performance goals |
| Maximum announced consideration | Up to 9.3 million | Required achievement of the specified milestones |
Contemporary EE Times reporting valued the initial stock portion at about $2.06 billion using a Broadcom share price of $222. If all milestones and related options were achieved, it estimated a possible total value of about $2.46 billion. Those dollar figures were transaction-time stock valuations, not a cash price, and the contingent portion was not guaranteed.
The SB-1: SiByte’s flagship MIPS core
SiByte’s central technology was the SB-1, a 64-bit superscalar MIPS core designed for network processing. Broadcom’s 2000 announcement described the following targets and simulated results:
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- Operation at up to 1.0 GHz.
- A quad-issue pipeline capable of issuing as many as four instructions per cycle under suitable conditions.
- Separate integrated 32K instruction and 32K data caches.
- Benchmark simulation above 2,200 Dhrystone 2.1 MIPS at 1.0 GHz.
The Dhrystone number was a simulation result reported by Broadcom, not an independent production-system benchmark. Real throughput depends on memory behavior, software, I/O and the networking workload.
Broadcom president and chief executive Henry T. Nicholas III characterized the technology as “the world’s fastest and lowest power MIPS industry-standard broadband processor technology.” The claim reflects Broadcom’s announcement language at the time and should not be read as a timeless ranking across every processor or benchmark.
What the Mercurian family and SB-1250 did
SiByte’s Mercurian family targeted high-speed LAN, metropolitan-area (MAN) and wide-area (WAN) equipment, VoIP gateways, optical networking and wireless communications. Its design emphasis was system integration: processing packets while coordinating memory and communications I/O on the same device.
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SB-1250 architecture
The SB-1250 was described as a dual-core MIPS64 system-on-chip. It integrated cache and I/O and was intended for demanding packet and control-plane tasks, including:
- Packet classification and queuing
- Packet forwarding
- Exception processing
- Routing
- Load balancing
Using two 64-bit MIPS cores allowed software to divide control and packet-processing work or run parallel tasks, although the practical benefit depended on the operating system, software architecture and I/O design.
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Later BCM1250 documentation
In a September 26, 2002 white paper, Broadcom documented the BCM1250/SiByte family as dual 64-bit MIPS systems scalable from 600 MHz to 1 GHz. The paper identified applications such as IP storage-area-network gateways, SAN routers, network-attached-storage systems and iSCSI cards. This later documentation shows how the SiByte technology was presented within Broadcom’s product family after the acquisition, but it does not change the original transaction terms.
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What happened to SiByte and the SB-1250?
SiByte ceased being an independent company as its processor technology was absorbed into Broadcom’s product organization. The technology continued under Broadcom branding, including the BCM1250 designation and related SiByte family documentation. The available announcements establish that product transition and later BCM1250 documentation, but they do not provide a complete product-by-product account of discontinuation dates, customer shipments or successor models.
For that reason, it is more accurate to describe the SB-1250 as a SiByte-origin design that appeared in Broadcom’s BCM1250 family than to claim a specific end-of-life date that is not documented here.
Why the acquisition mattered in network processors
SiByte’s proposition combined a standard MIPS instruction set with unusually high integration for its era. The relevant evaluation criteria were:
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- Processing model: the SB-1 was a single 64-bit superscalar core, while the SB-1250 used two MIPS64 cores.
- Integration: on-chip cache and communications I/O reduced the number of external components.
- Network workload fit: packet classification, forwarding, routing, queuing and exception handling were explicit targets.
- Performance and power: Broadcom emphasized 1.0 GHz operation and low-power positioning, while the published Dhrystone figure was a simulation.
- Commercial evidence: design wins and contracts exceeding 1.3 million units gave Broadcom a customer and revenue pipeline to combine with its own portfolio.
- Economics: the consideration could reach 9.3 million Broadcom shares, with much of the value contingent on performance.
Cisco engineering vice president John Wakerly summarized the appeal as a combination of CPU performance, memory and communications-I/O integration for next-generation network equipment. In practical terms, Broadcom was buying a processor roadmap that could make its component portfolio more central to complete networking platforms.
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