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What is the difference between SOT-MRAM and SRAM?
SRAM stores data in an electronic circuit that must remain powered to retain its state. It is fast, which makes it useful for processor caches, but it loses data when power is removed and consumes standby power while idle. SRAM bit-cell scaling also limits how much cache fits in a given area. imec describes those scaling constraints as a reason to look for alternatives.
SOT-MRAM stores data magnetically in a magnetic tunnel junction (MTJ), so it can retain information without power. An MTJ has a fixed magnetic layer, a free magnetic layer and a thin magnesium-oxide (MgO) barrier between them. The relative magnetization of the two layers changes the junction’s resistance, encoding the stored bit.
The key distinction between SOT-MRAM and STT-MRAM is how they write that bit. STT-MRAM sends write current through the MTJ. SOT-MRAM sends an in-plane current through an adjacent spin-orbit-coupling layer, often a heavy metal, to switch the magnetic state. That separates the write path from the MTJ read path. In principle, it lets a circuit sense the bit without exposing the tunnel barrier to the write current, supporting read stability and endurance.
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| Characteristic | SRAM | STT-MRAM | SOT-MRAM |
|---|---|---|---|
| How it stores data | Electronic state; volatile | Magnetic state in an MTJ; non-volatile | Magnetic state in an MTJ; non-volatile |
| Write path | Electronic circuit; exact write current and energy not stated in the cited sources | Write current passes through the MTJ | In-plane current in an adjacent spin-orbit-coupling layer, separate from the MTJ read path |
| Standby power | Requires power to retain data; exact leakage figure not stated in the cited sources | Non-volatile; comparative standby-power figure not stated in the cited sources | Non-volatile, with low standby power and negligible leakage described by imec; no comparative figure stated |
| Switching speed | Described as ultrafast by imec; a comparable number is not stated in the cited sources | IEEE IRDS reports 3–10 ns switching at 7 MA/cm² in its 2024 roadmap | IEEE IRDS reports sub-ns writing at 20–40 MA/cm² in its 2024 roadmap |
| Write current or energy | Comparable figures not stated in the cited sources | Roadmap current density is 7 MA/cm²; write energy is not stated in the cited sources | Roadmap current density is 20–40 MA/cm²; lowering write energy while keeping sub-ns operation is an identified challenge |
| Endurance | Comparable cycle figure not stated in the cited sources | Comparable cycle figure not stated in the cited sources | imec reported endurance above 1012 cycles for a particular architecture in 2022; that result should not be generalized to every SOT-MRAM cell |
| Area and density | SRAM scaling constraints limit bit density, according to imec | Comparative cell-area figure not stated in the cited sources | Extra access devices and a separate write track can increase cell area; comparative cell-area figure not stated in the cited sources |
| Manufacturing readiness for cache | Established cache technology | MRAM products and evaluation hardware exist, but the cited portfolio is STT-MRAM | Manufacturing test platforms support SOT-MRAM development; a broadly available SOT-MRAM cache product is not established |
The figures in the table are not an apples-to-apples benchmark: the switching numbers are from the IEEE International Roadmap for Devices and Systems’ 2024 roadmap, while the endurance figure is from one imec architecture report. The sources do not provide a common silicon test comparing all three memory types on latency, energy or cell area.
Can SOT-MRAM replace SRAM cache?
Potentially, but the case is strongest for larger on-chip caches, such as L3 or last-level cache, rather than an immediate replacement for every SRAM level. A larger cache has room for a modest performance trade-off if denser, non-volatile storage can reduce idle power or enable more capacity in the same area. Replacing L1 or L2 is harder because those levels place greater pressure on latency and write energy.
A 2024 review in npj Spintronics frames the intended roles this way: “SOT-MRAM is aimed at replacing SRAM due to its fast operation, while STT-MRAM is targeted for high-performance and high-density embedded DRAM applications.” That is a technology-positioning assessment, not evidence that SOT-MRAM has already replaced SRAM in commercial processors.
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Is SOT-MRAM faster than STT-MRAM?
The 2024 IEEE roadmap lists sub-nanosecond SOT writing at 20–40 MA/cm², compared with 3–10 ns STT-MRAM switching at 7 MA/cm². On those roadmap figures, SOT-MRAM has the faster write-switching range, but it uses a higher current density. The figures do not establish that every SOT-MRAM device is faster than every STT-MRAM device, nor do they compare full cache access latency, read speed or total system performance.
Fast switching alone does not settle whether a memory is suitable for a cache. The write current and energy, read stability, cell area and integration with processor circuitry all matter alongside latency.
Does SOT-MRAM reduce cache leakage power?
Its non-volatility removes the need to keep the magnetic data powered merely for retention, giving SOT-MRAM a path to lower standby power than volatile SRAM. imec describes the technology’s potential benefits as including “low standby power consumption” and “negligible leakage.” Those are technology-level benefits, not a measured reduction for a particular commercial cache: the cited sources do not provide a matched SRAM-versus-SOT-MRAM cache leakage figure.
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What evidence shows SOT-MRAM is moving closer to cache use?
Roadmap switching figures
The 2024 IEEE International Roadmap for Devices and Systems records sub-nanosecond SOT writing at 20–40 MA/cm². It also identifies reducing write energy while retaining sub-nanosecond operation as a key challenge for cache applications. The roadmap numbers describe switching, not the complete access time or energy of a processor cache.
Endurance in an imec architecture
In a 2022 architecture report, imec reported endurance above 1012 cycles for the demonstrated design. This is evidence for that architecture, not a guaranteed endurance specification for SOT-MRAM generally or for a product available to buyers.
Processor-level simulation
A 2024 J-STAGE study modeled an NVDLA deep-learning processor with a 512-KB buffer and cache options from 1 MB to 8 MB. In the modeled design, SOT-MRAM allowed double the capacity in the same area. Replacing both the buffer and cache produced 18.6% lower simulated energy, a 17.9% reduction in the study’s reported speed metric, and more than 36.4% better performance per unit area.
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These are workload-specific simulation results, not measurements from a fabricated processor. The reported speed metric fell, so the energy and area gains should not be read as proof that the design was faster overall.
Newer orbital-Hall materials
A 2025 Nature Communications study tested ruthenium orbital-Hall layers against platinum in stacks using a perpendicular [Co/Ni]3 ferromagnet. Across more than 250 tested devices, the Ru layers showed about 30% higher damping-like torque efficiency, about 20% lower switching current and more than 60% lower switching power than Pt in those tested stacks. This materials-level result could help address switching costs, but it does not demonstrate a commercial cache chip.
What still blocks adoption in processor caches?
- Write current and energy: The higher current density in the roadmap’s fast SOT switching range underlines the challenge. A cache design needs to meet its speed target without making writes too energy-intensive.
- Reliable field-free switching: Deterministic switching without an external magnetic field is necessary for dense processor integration. For perpendicular magnetic anisotropy (PMA) devices, achieving it generally requires symmetry-breaking structures or material engineering.
- Cell area: Conventional SOT layouts use a separate write track and extra access devices. That can offset the density advantage sought for cache. Voltage-controlled magnetic anisotropy (VCMA)-assisted and two-terminal concepts are being studied to reduce area and transistor count.
- BEOL-compatible manufacturing: The magnetic stack must fit within the back-end-of-line (BEOL) process, including its thermal limits and interconnect flow, without disrupting CMOS manufacturing.
- Perpendicular-anisotropy scaling: PMA is attractive for scaling, but it must be paired with a practical way to switch reliably without an external field.
When will SOT-MRAM be commercially available?
The cited evidence does not establish a launch date for a purchasable SOT-MRAM cache, nor does it support a reliable prediction of when one will appear. There is relevant industrial infrastructure: Hprobe’s IBEX product family offers test platforms for MTJs and memory bit cells covering STT-MRAM, SOT-MRAM and VC-MRAM, including wafer-acceptance and functional testing. That shows SOT-MRAM is part of the manufacturing test ecosystem; it is not itself a memory chip or cache product.
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Are there SOT-MRAM chips or development boards I can buy?
The available evidence does not identify a verified retail SOT-MRAM chip, module or development board suitable as cache hardware. Everspin and distributors offer MRAM evaluation hardware, including the MR25H00-EVAL, a 4-Mbit SPI MRAM board, but the cited Everspin portfolio is STT-MRAM. It is an adjacent technology, not an SOT-MRAM development board or a demonstration of SOT-MRAM cache.
Industrial wafer and bit-cell test equipment is aimed at manufacturers and labs, not ordinary development-board use. There is therefore no honest retail SOT-MRAM cache item to recommend on the evidence available.
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