There is no universally best memory for an IoT device. The right choice depends on the data it must hold, how quickly the device must use it, whether that data must survive sleep or power loss, and how the whole system behaves while active, idle, and waking. A memory chip’s specifications alone cannot tell you how much energy the finished device will use.
Start with the workload and power states
Memory design is a system decision. The MCU’s internal memory, any external memory, the controller and bus, cache behavior, firmware placement, and sleep strategy all affect response time and energy. Begin by identifying what the device does—not by ranking memory types in isolation.
- Working data: Identify the buffers, sensor samples, intermediate results, and application state the device needs while running.
- Response-time requirement: Set acceptable average and worst-case access latency for the tasks that matter.
- Persistence: Decide which information must remain available through sleep, a reset, or complete power loss.
- Power behavior: Describe active, idle, sleep, and wake periods, including how often the device wakes and how long it stays asleep.
- Capacity and integration: Account for memory size, interface and pin use, software complexity, security needs, and total system cost.
Always-on equipment may prioritize performance within its power and cost budget. Battery-operated equipment typically gives more weight to energy use and form factor. These are starting points, not a substitute for measuring the actual workload. The IETF’s RFC 9556, Internet of Things (IoT) Edge Challenges and Functions, notes that constrained IoT devices can face reliability, performance, energy, security, and privacy challenges because they have limited storage and processing power.
Choose memory by the job it needs to do
| Memory type | Typical role | What to evaluate |
|---|---|---|
| Internal SRAM | Volatile working memory for active code and data. | Capacity, access latency, predictable timing, retention options, and standby power. Low-power SRAM techniques can increase access delay, so test the selected implementation. |
| External PSRAM | Volatile capacity expansion for buffers, graphics, or temporary data on compatible systems. | Read/write latency and throughput, active and standby power, retention, wake time, bus contention, interface and pin cost, and exact MCU/module compatibility. |
| Embedded flash | Nonvolatile firmware and persistent data integrated with the MCU. | Capacity, latency, energy, density-related cost, and the requirements of the selected MCU. |
| External SPI flash | Nonvolatile capacity expansion for larger code or data sets. | Its interface and integration overhead, access speed, energy, and whether caching can reduce repeated external accesses. |
| RRAM or tightly coupled memory | Platform-specific nonvolatile storage or fast, predictable access. | Availability and characteristics on the particular MCU; neither is a universal substitute for SRAM or flash. |
Internal SRAM for constrained working data
Internal SRAM can be a strong fit for data that needs fast, predictable access, provided its capacity and power behavior fit the design. The Embedded.com article on this topic highlights an important trade-off: special low-power standby techniques for SRAM can increase access delay. Measure the access behavior of the selected device and configuration rather than assuming that a low-power mode preserves normal response time.
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Platform guidance is specific to the chip family. Infineon, for example, describes internal memories on its PSOC Edge platform as supporting low-power and high-performance designs, and identifies tightly coupled memory as an option for faster, predictable access. That is guidance for that platform, not a general guarantee for every MCU.
External PSRAM for volatile capacity
PSRAM can add working capacity without making that data nonvolatile. Silicon Labs describes QSPI PSRAM on its SiWx917 platform for buffers, graphics, and temporary storage. Its description combines a DRAM core and self-refresh with an SRAM-like interface; the specific SiWx917 connection uses QSPI.
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External PSRAM is useful only if its capacity gain is worth the system costs. Check that the MCU supports the exact part and operating modes, then assess the added interface, pin use, contention, access timing, and active and standby energy. Verify whether contents survive the chosen standby mode and how long the device takes to resume access. Silicon Labs advises benchmarking reads and writes in the real power states used by the application.
Flash for information that must persist
Flash is nonvolatile, making it suitable for firmware and data that must survive power loss. Renesas describes embedded flash as an integrated, lower-latency and lower-power option for many lower-to-mid-range IoT applications, while noting that higher density can increase cost pressure. Infineon describes external SPI flash as a way to expand space for code or data, with trade-offs in speed and power efficiency. These are vendor-specific design observations; compare the actual MCU and flash devices in your application.
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Platform-specific alternatives
Infineon documents RRAM and tightly coupled memory options on PSOC Edge. Treat these as features of that platform and verify the implementation, capacity, and power behavior of the part you intend to use. Do not assume that an option or its benefits carry over to unrelated MCU architectures.
Account for memory placement, caching, and transfers
External memory may increase capacity while adding interface activity and access overhead. If code or data is accessed frequently, cache can reduce the number of external-memory accesses; Infineon recommends instruction caching for external memory use on its documented platform. The energy benefit depends on the access pattern and cache behavior, so validate it on the target.
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DMA may let the processor sleep while a transfer runs, but it does not automatically reduce total system energy. Include the memory interface, controller, and any time spent waiting or waking in the measurement. On Silicon Labs’ SiWx917, the vendor recommends QSPI memory-mapped auto mode where possible to reduce access latency, and cautions against unnecessary deep-power-down cycles that may lose contents or add wake overhead. Apply those details to that platform; use the selected memory vendor’s guidance for other systems.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Keep only necessary state through sleep
Retaining all volatile memory can simplify resume, but it may consume more standby power than the device’s energy budget allows. Conversely, shutting down memory can require restoration or reinitialization and delay the next task. Decide which application state must be immediately available and which can be reconstructed, reread, or discarded.
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- Keep only the state needed for fast resume in retained volatile memory.
- Use device-supported low-power modes and RTC wakeups where appropriate.
- On platforms that support it, retain only the required SRAM blocks and disable unused domains or external-memory interfaces.
- Check retention and wake timing for the exact memory part and mode; do not infer retention from the memory type alone.
AWS IoT Lens recommends a low-power mode that retains volatile memory when rapid restoration of application state is needed. Infineon documents selective SRAM-block retention and the disabling of unused domains or interfaces on PSOC Edge. These are design approaches, with implementation dependent on platform support.
Use device specifications as examples, not universal targets
Published figures can illustrate how different the options are across platforms, but they are not comparable benchmarks unless measurement conditions and workloads match.
| Documented example | What the source specifies | How to interpret it |
|---|---|---|
| Espressif ESP8684 Series Datasheet v2.3 | 5 µA listed deep-sleep consumption; four operating modes (Active, Modem-sleep, Light-sleep, Deep-sleep); 272 KB SRAM, including 16 KB for cache; in-package flash variants of 2 MB and 4 MB. | These are ESP8684-family specifications, not a general IoT target or a measurement of memory energy in isolation. |
| Infineon PSOC Edge application note, last updated 2025-12-16 | 512 KB + 512 KB low-power-domain SRAM; 5120 KB high-performance-domain System SRAM; a 512 KB RRAM option; 256 KB each of CM55 instruction and data tightly coupled memory. | These are architecture figures for the documented PSOC Edge MCU, not typical IoT capacities. |
The sources do not establish a harmonized cross-vendor benchmark or a universal memory-versus-power relationship. Compare candidates under the same conditions rather than using a single device’s specification to rank memory technologies.
Measure the finished design on its target hardware
- Define representative tasks. Include the real sensor processing, buffering, filtering, and communications that drive memory access. Specify required capacity and acceptable response time.
- Choose comparable configurations. Compare the memory options that are compatible with the MCU and board. Record the cache state, access pattern, and sleep policy for each.
- Normalize test conditions. Keep voltage, clock, temperature, burst pattern, and sleep duration consistent so that the measurements answer the same question.
- Measure timing and energy across states. Profile latency and energy during active work, idle, sleep, and wake. Include reads, writes, transfers, and the time needed to restore or reinitialize data.
- Check the constraints beyond the benchmark. Confirm capacity, retention, wake time, pin and interface use, software configuration, security needs, and total component and system cost.
- Profile and tune the final firmware. Test the actual board and memory device, then verify that caching, DMA, selective retention, and low-power modes behave as expected in the deployed workload.
AWS IoT Lens recommends evaluating energy efficiency and latency with representative workloads and optimizing under both runtime and idle conditions. A board-level measurement matters because firmware, buses, memory devices, and sleep policy interact in ways that a part label or isolated specification cannot capture.
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