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In 2006, ARM offered the ARM996HS, a licensable 32-bit processor core built with asynchronous, or “clockless,” logic. The announcement did not mark the invention of clockless computing; its significance was bringing a clockless ARM core to a commercial licensing offering. Microprocessor Report described it as the first commercially available 32-bit processor core implemented in asynchronous logic.
The ARM996HS was semiconductor IP for chip designers, not a retail processor or ready-to-use board. ARM handled licensing, while Handshake Solutions worked on the asynchronous design and implementation flow.
What “clockless” meant in the ARM996HS
A conventional synchronous processor coordinates state changes using a global clock. The ARM996HS instead used local request-and-acknowledge handshakes between modules: a pipeline stage signaled that data was ready, and the next stage signaled when it had accepted it. The Hot Chips 18 presentation describes four-phase handshaking and distributed activation across a five-stage pipeline.
That approach can make circuit activity follow the work being done rather than a fixed global clock cadence. “Clockless” did not mean that every part of a finished chip lacked timing signals. The presentation describes synchronous AHB-Lite interfaces and integration with synchronous ASIC designs and standard synchronous RAM.
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What the ARM996HS included
The ARM996HS was a 32-bit ARMv5TE RISC core with an ARM9E-like five-stage integer pipeline. Its described features included:
- 16-bit Thumb and 32-bit ARM instruction sets
- Harvard bus architecture and dual AMBA 3 AHB-Lite interfaces
- Fast 32-bit multiply-accumulate and hardware divide
- Memory-protection unit and nonmaskable interrupts
These are specifications of the historical core described in the 2006 technical presentation, not a claim about a current ARM product.
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Why ARM and Handshake Solutions pursued asynchronous logic
The developers presented lower power consumption, reduced current peaks and electromagnetic emissions, and adaptation to environmental changes as potential advantages. The underlying idea is that local handshake circuits respond to completed work and operating conditions rather than relying entirely on a fixed clock period. These were engineering goals and developer-reported results, not guarantees for every implementation, workload, or chip.
The presentation also cautioned that performance depends on operating conditions. Although handshake circuits adapt to changes such as temperature and supply voltage, the design could not simply be slowed to imitate worst-case timing without an added mechanism. The described HT-Metrics peripheral could synchronize pipeline operation to external events and reduce speed to mimic worst-case conditions.
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How it compared with the ARM968E-S
ARM and Handshake Solutions reported the following historical comparison with the synchronous ARM968E-S in their 2006 Hot Chips presentation. The figures came from post-layout simulation, not an independent laboratory test, and should not be treated as a modern or broadly applicable benchmark.
| Measure | ARM996HS presentation figure | Comparison and context |
|---|---|---|
| Power | Reported as consuming 2.8 times less power than the ARM968E-S | Developer-reported result from the stated implementation comparison |
| Current peaks | Reported reduction by a factor of 2.4 | Developer-reported result from the stated implementation comparison |
| Hardware divide | 13 equivalent cycles | 36 cycles for the ARM968E-S, according to the same presentation |
| Area | Less than 0.59 mm² | Compared with 0.69 mm² for the ARM968E-S in the presentation’s implementation context |
The post-layout simulation used an Artisan Sage-X 0.13 μm TSMC process. The presentation identified nominal conditions as 1.2 V and 25°C, and worst-case conditions as 1.08 V and 125°C. The reported values belong to that historical process and comparison; they do not establish how the cores would compare in another process, implementation, or workload.
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How the core was intended to reach chip designers
The collaboration between ARM and Handshake Solutions was announced in October 2004, and the ARM996HS was announced in February 2006. ARM Ltd handled licensing. The presentation describes delivery as a firm core targeted to a customer’s standard-cell library, with hardening scripts and design-for-test support. The core could be integrated into a synchronous ASIC.
Handshake Solutions used its HASTE design-entry language and a library of handshake components. Its described flow produced a targeted Verilog netlist and backend scripts for the licensee; the presentation said the internal flow was hidden from the licensee. These details describe the historical delivery model, not present-day licensing terms.
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Applications proposed in the 2006 announcement
The developers listed automotive systems, low-cost consumer electronics, wireless devices, medical implants, smartcards, and sensor networks as possible application areas. These were proposed use cases, not evidence that the ARM996HS shipped in products for those markets.
The presentation also claimed that Handshake Technology was already used in 25 chip designs and more than 100 million ICs. Those totals are claims made by Handshake Solutions in 2006, not independently verified figures.
Is the ARM996HS available today?
The historical sources establish that the ARM996HS was offered for licensing in 2006. They do not establish whether it remains licensable today, so its current availability cannot be confirmed from this evidence. It was processor IP for semiconductor companies, not a consumer product with a retail price, compatible board, or replacement part.
Quick Recap
Sources
- Microprocessor Report / In-Stat, “ARM and Handshake Solutions Debut Clockless Processor Core,” February 20, 2007
- Arjan Bink and Richard York, “ARM996HS: The First Licensable, Clockless 32-bit Processor Core,” Hot Chips 18, 2006
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