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Arm Cortex-A320 is an Armv9.2-A processor core designed for embedded and IoT systems. It can run machine-learning work on its own CPU using NEON and SVE2 vector instructions; pairing it with an Ethos-U85 neural processing unit (NPU) can accelerate supported neural-network operations. The NPU is optional, and neither the core’s capabilities nor Arm’s performance claims establish that a finished product or retail board is available.
What Cortex-A320 is—and what it is not
Cortex-A320 is processor intellectual property (IP) that chip designers can incorporate into a system-on-chip (SoC), not a standalone consumer processor that an end user installs in a computer. Arm describes it as its smallest Armv9 implementation and an ultra-efficient core for IoT. The launch article identifies it as an AArch64 core based on Armv9.2-A. Arm’s Cortex-A320 product page gives its current product positioning.
That distinction matters: Cortex-A320 describes a CPU design, while a usable device also depends on the SoC and the rest of the system, including memory, software, peripherals, power design, and any accelerator. A core’s advertised capability is not by itself a guarantee of performance, power consumption, or support in a particular product.
How the CPU and an NPU divide AI work
Cortex-A320 includes NEON and SVE2 vector processing. These capabilities can accelerate machine-learning operations executed on the CPU, alongside the core’s general-purpose software workloads. So a system can run some ML work without an NPU.
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In a system that pairs Cortex-A320 with Arm’s Ethos-U85 NPU, supported neural-network operations can be offloaded to the NPU. Arm says the NPU can be driven directly by Cortex-A320, without a separate Cortex-M-based ML island. If an operator or datatype is not supported by the NPU, Arm says that work can fall back to the CPU. The actual division depends on the model, its operators and datatypes, and the software stack; an NPU does not automatically run every part of every model.
In practical terms, the CPU provides flexible execution and can handle supported CPU-side ML work or NPU fallback, while the NPU is a specialized option for accelerating the neural-network operations it supports. Whether adding one is worthwhile depends on the workload and the complete system’s constraints, not simply on whether a product is described as “AI.” Arm’s Cortex-A320 launch article details the core and its relationship with Ethos-U85.
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What Arm’s performance figures actually say
Arm’s February 2025 launch article reports workload-specific comparisons and a configured peak figure. These are Arm claims, not independent benchmarks of a finished Cortex-A320 product. They should not be read as guaranteed gains in a shipping device, general application speed, latency, or energy efficiency.
| Arm-reported result | How to interpret it |
|---|---|
| Up to 10× ML processing uplift versus Cortex-A35 | Measured in int8 General Matrix Multiplication (GEMM); not a blanket 10× improvement across ML models or applications. |
| More than 30% scalar performance uplift versus Cortex-A35 | Reported for SPECINT2K6, a particular benchmark; it is not a universal application-speed result. |
| Up to 6× higher ML performance versus Cortex-A53 | Arm discusses newer datatypes, including BF16, and new dot-product and matrix-multiplication instructions. The claim is not a general result for every workload. |
| Up to 8× higher GEMM performance versus Cortex-M85 | A GEMM-specific CPU comparison, not a comparison of complete systems. |
| Up to 256 GOPS | Arm’s figure for a quad-core Cortex-A320 at 2 GHz, calculated using 8-bit multiply-accumulate operations per cycle. It is a configured CPU capability, not a system-level power or latency measurement. |
| 8× ML performance versus an earlier Cortex-M85-based platform | Arm’s announcement describes a platform comparison; it should not be conflated with a CPU-only Cortex-A320 comparison. |
| Up to 70% improvement attributed to Arm Kleidi | Arm reports this for a Tiny Stories small-language-model run with Llama.cpp. The result is specific to that model and runtime context. |
The figures do not establish how a particular product will perform. No independent benchmark or measured energy-consumption figure for a finished Cortex-A320 device is established by the cited materials. Arm also says the memory system can enable on-device models larger than one billion parameters, but does not specify a universal memory configuration, quantization, latency, or application quality for that statement. It is not evidence that any Cortex-A320 system can run a particular large model successfully.
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Architecture and intended workloads
Arm’s launch article describes Cortex-A320 as a single-issue, in-order core with an optimized eight-stage pipeline. It specifies clusters of one to four cores with DSU-120T, up to 64 KB of L1 cache and 512 KB of L2 cache, and a 256-bit AMBA5 AXI external-memory interface. These are launch-article specifications; engineers making implementation decisions should consult the current technical reference manual and the configuration details for the design they are evaluating.
Arm identifies smart cameras, industrial automation, smart-home systems, IoT endpoints, gateways, and advanced human-machine interfaces as target applications. These examples describe where the IP is aimed, not confirmed products using it. Arm’s Armv9 edge-AI platform announcement provides the broader platform framing.
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How to decide whether CPU-only or CPU-plus-NPU fits
There is no neutral, quantitative comparison in the cited material that settles the choice for every system. Evaluate the intended model and the full implementation against these design questions:
- Operator coverage: Which model operations and datatypes are supported by the NPU and its software tools? Identify CPU fallback paths rather than assuming complete offload.
- Performance and latency: Test the workload and end-to-end response time on the intended configuration. A peak operation rate or a benchmark uplift does not establish application latency.
- Memory: Check model size, runtime memory requirements, available capacity, and bandwidth. The core alone does not specify the memory available in a product.
- Energy, area, and cost: Compare measured requirements for the complete SoC and product. The cited claims do not establish a finished-device energy result or a universal cost trade-off.
- Software and integration: Confirm runtime, compiler, driver, operating-system, and model-support requirements, as well as the engineering complexity of adding and validating an accelerator.
Arm’s edge AI solution selection guide places Cortex-A, Cortex-M, and Ethos-U approaches in a broader selection context. The right choice depends on workload coverage and system constraints, not on a single headline performance number.
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Development resources and product availability
Arm describes Corstone-1000 with Cortex-A320 as configurable subsystem and system IP for Linux-capable SoCs, aimed at low-power MPUs, wearables, IoT endpoints, gateways, and NPU-based edge-AI applications. Arm’s support page for Corstone-1000 with Cortex-A320 provides subsystem and reference-software context.
Arm’s IoT Fixed Virtual Platforms support listing describes a multicore Cortex-A320 cluster connected directly to Ethos-U85 and includes a software-stack entry dated June 30, 2026. A Fixed Virtual Platform is an evaluation resource, not proof of a retail development board or an add-on NPU module.
Arm announced that Cortex-A320 would be available through Arm Flexible Access in November 2025, with Ethos-U85 to follow in early 2026. Those dates have passed; the Arm Flexible Access announcement does not establish current program terms or eligibility. The cited materials establish processor IP and development resources, but do not establish a consumer board, retail chip, compatible accessory, or specific shipping device.
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