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The interview is best read as a dated strategic account of Intel’s plan—not as a current 2026 roadmap or proof that every target had already been achieved.
What the AnandTech interview was
The article appeared in Ian Cutress’s AnandTech author archive on February 18, 2022, under the headline “AnandTech Interview with Dr. Ann Kelleher: EVP and GM of Intel’s Technology Development.” It was conducted around Intel’s accelerated process-roadmap announcement; AnandTech’s associated coverage describes Kelleher speaking ahead of that announcement.
That context matters. The exchange was not an independent audit of Intel’s manufacturing results. It was a management interview explaining the assumptions, technologies and organizational changes behind Intel’s announced recovery plan.
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- Next‑Gen Platform Support: Compatible with Intel 800 Series Chipset‑based motherboards with LGA1851 Socket enabling PCIe 5.0/4.0 and high‑speed DDR5 memory (up to 7200 MT/s).
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Who Ann Kelleher was at Intel
Kelleher brought an unusual combination of process-development and factory experience. AnandTech described a career that began in process research and extended across roughly 26 years at Intel, including process-engineering and fab-management work associated with facilities in Ireland, Arizona and New Mexico. She later moved into senior manufacturing and technology-development leadership.
That background made her more than a roadmap spokesperson. Her remit connected laboratory process work with high-volume manufacturing, supplier coordination, yield, packaging and the practical problem of turning a demonstrated technology into a repeatable commercial process. The broad career description is supported by AnandTech’s contemporary coverage; individual job titles and dates should not be inferred beyond that account.
The manufacturing problem Intel was trying to reverse
Intel was attempting to recover from delays in the transition from 14 nm to 10 nm while TSMC had moved more quickly into advanced-node production. Pat Gelsinger’s IDM 2.0 strategy responded by combining three approaches:
- continued internal manufacturing;
- selective use of external manufacturing partners; and
- the expansion of Intel Foundry Services for outside customers.
Technology Development therefore had to solve more than transistor performance. Intel needed a process that could be developed on schedule, yield at volume, support product teams, compete on cost and power, and offer a credible platform to foundry customers. A node announcement by itself could not resolve all of those issues.
An earlier interview with then-CEO Bob Swan provides additional context for Intel’s willingness to consider outside manufacturing while retaining strategic control: AnandTech’s Bob Swan roundtable.
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Intel’s accelerated process roadmap
Intel’s associated 2021 announcement presented process leadership as a goal for 2025, with performance per watt as the central headline metric. The roadmap used generational brand names, not literal measurements of transistor dimensions.
| Node | Role in the announced roadmap |
|---|---|
| Intel 4 | Successor to Intel 7 and a major step toward extensive EUV use. |
| Intel 3 | Fast-follow generation with additional performance and library improvements; Intel reported an 18% performance-per-watt improvement over Intel 4. |
| Intel 20A | Generation introducing RibbonFET gate-all-around transistors and PowerVia backside power delivery. |
| Intel 18A | Further refinement intended to support Intel’s stated 2025 process-leadership target and advanced EUV capability. |
These schedules and the 18% figure were Intel’s announced claims as reported by AnandTech, not neutral measurements established by the interview. “Intel 4,” “Intel 3,” “20A” and “18A” should not be treated as one-to-one equivalents of TSMC or Samsung node labels. Meaningful comparison requires examining transistor density, performance, power, design rules, libraries, yield, cost and product availability.
Related AnandTech topic pages provide the contemporary roadmap context for Intel 4, Intel 7, Intel 20A and IDM 2.0.
RibbonFET and PowerVia explained
RibbonFET: Intel’s gate-all-around transistor
Earlier FinFETs use a fin-shaped channel controlled by a gate on several sides. A gate-all-around transistor surrounds the channel more completely, improving electrostatic control as dimensions shrink. Intel called its implementation RibbonFET.
The architecture was intended to provide additional scaling headroom and support future power, performance and density gains. It did not guarantee superior chips by itself: voltage, frequency, standard-cell libraries, interconnect, design choices, yield and packaging all influence the final product.
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PowerVia: backside power delivery
PowerVia was Intel’s backside-power approach. By moving much of the power-delivery network away from the front-side signal-routing structure, Intel expected to create more routing space, shorten or improve power paths, and potentially improve power integrity and density.
Backside power also creates a difficult integration problem. It affects wafer processing, design rules, tooling, verification and manufacturing yield. A successful demonstration would not automatically establish acceptable cost, volume production or broad ecosystem support.
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Kelleher described Intel’s recovery as an organizational and coordination challenge as well as an engineering one. AnandTech attributed several changes to her leadership:
- a revised approach to suppliers and greater use of ecosystem learning;
- changes within Technology Development;
- more modular process design;
- contingency planning and a streamlined development organization; and
- clearer technical leadership, including Sanjay Natarajan in logic development and Babak Sabi in assembly and test development.
Modularity was intended to reduce risk. A fast-follow node could reuse proven portions of an earlier process while introducing targeted improvements, rather than rebuilding every element at once. The trade-off is that an aggressive cadence creates more simultaneous development programs, tighter equipment and materials coordination, and greater pressure on product and design-enablement teams.
The plan also linked front-end process work with advanced packaging, including EMIB and Foveros. Chiplets, packaging, memory and system integration increasingly determine real product results, so packaging could not be treated as an afterthought to transistor scaling.
Rank #4
- Game Without Compromise. Play harder and work smarter with Intel Core 14th Gen processors
- 20 cores (8 P-cores plus 12 E-cores) and 28 threads. Discrete graphics required
- Up to 5.6 GHz with Turbo Boost Max Technology 3.0 gives you smooth game play, high frame rates, and rapid responsiveness
- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
Why performance per watt was not the whole story
Intel framed leadership primarily around performance per watt while acknowledging that peak performance remained important. That metric is useful, but its meaning depends on the test boundary:
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- Was the comparison made at transistor, library or complete-chip level?
- Was frequency, power or area held constant?
- Were packaging and memory included?
- Was the result a projection, a best-case demonstration or a shipping-product measurement?
- Which competitor process and design conditions formed the baseline?
An 18% performance-per-watt claim for Intel 3 over Intel 4 therefore cannot be generalized to every product or workload. A process can improve efficiency while making trade-offs in peak frequency, die area, cost or yield.
What IDM 2.0 meant for Intel Foundry
Intel’s foundry ambition raised a second execution test: outside customers had to trust Intel with designs, schedules and supply commitments. That required more than wafers. Customers would need mature process-design kits, electronic-design-automation support, intellectual-property libraries, packaging options, capacity, predictable yields and long-term supply confidence.
Internal fabs offered tighter coordination between Intel’s product and process teams, potential supply flexibility and strategic control. External manufacturing offered access to mature ecosystems and a way to keep products moving when an internal node was late. Outsourcing could, however, reduce margins, consume constrained capacity, require redesigns and complicate validation, packaging and supply-chain management.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to judge the roadmap claims
The interview should be separated into four evidence levels:
Best Value
- Game without compromise. Play harder and work smarter with Intel Core 14th Gen processors
- 24 cores (8 P-cores plus 16 E-cores) and 32 threads. Integrated Intel UHD Graphics 770 included
- Leading max clock speed of up to 6.0 GHz gives you smoother game play, higher frame rates, and rapid responsiveness
- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
- Intel’s announcements: schedules, node names, technology descriptions and performance-per-watt targets.
- Kelleher’s explanation: how Intel said its organization, suppliers and development methods would improve execution.
- Technical demonstrations: evidence that a transistor or process feature worked under stated conditions.
- Commercial execution: high-volume yield, cost, product availability, customer adoption and sustained supply.
Meeting a node date would not by itself prove manufacturing leadership. A process might be technically ready but yield poorly, lack enough capacity, arrive too late for product designs, or be limited by packaging and design enablement. Conversely, a company could ship a product while still falling short of the broader leadership claim.
What the interview gets right—and what it leaves open
The interview’s enduring value is that it presents Intel’s comeback as a manufacturing-system problem. Supplier relationships, fab operations, packaging, design tools, product schedules and foundry trust all had to move together.
Its limits are equally important. The February 2022 conversation could explain Intel’s intent, but it could not independently verify the 2025 target, establish parity with a specific TSMC or Samsung node, or prove that RibbonFET and PowerVia would automatically produce better commercial CPUs. It should not be used as evidence of Intel’s current 2026 responsibilities or strategy.
Bottom line
AnandTech’s interview with Dr. Ann Kelleher captured Intel at a pivotal point: the company was trying to restore process credibility through a faster node cadence, new transistor and power-delivery technologies, modular development and IDM 2.0’s combination of internal, external and foundry manufacturing. Its central lesson is that process leadership depends on execution across the entire manufacturing and product ecosystem—not on a node name or roadmap date alone.
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