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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchA Ruthroff transformer can deliver a useful broadband impedance transformation with very little hardware, but its ideal ratio is only the starting point. A 1:4 design has a 1:2 voltage ratio, yet its upper-frequency response is controlled by transmission-line delay, not just core inductance. The practical design sequence is to choose the source and load impedances, set the line impedance near their geometric mean, control electrical length and parasitics, then verify return loss, insertion loss, phase, balance, power and common-mode current. An equal-delay modification can extend the useful band, while Guanella or catalog transformers may be better choices when balance, repeatability or extreme bandwidth dominates.
What a Ruthroff transformer does
A Ruthroff transformer is a transmission-line transformer in which a bootstrapped line arrangement makes voltage contributions add or subtract while the line currents remain constrained by the transmission-line structure. The familiar 1:4 impedance transformer produces a 1:2 voltage ratio and a 2:1 current ratio:
Rin = 4RL
- 50 Ω load → 200 Ω input
- 200 Ω load → 800 Ω input
- 12.5 Ω load → 50 Ω input
The same topology can be wired as an unun or as a balun, depending on which terminals are grounded and how return currents are controlled. A balanced port has neither terminal tied to ground; an unbalanced port has one side referenced to ground. Calling every 4:1 transmission-line transformer a balun is therefore misleading. Mini-Circuits’ RF transformer application note defines these port and measurement terms in detail.
Typical uses include broadband matching, voltage step-up or step-down, balanced-to-unbalanced conversion, DC isolation where the winding arrangement permits it, and related combining or splitting functions.
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Ruthroff versus a lumped magnetic transformer
At low frequency, a transformer can be approximated as coupled inductors. That model predicts the nominal ratio but conceals the delay between points along the winding. At RF, each conductor pair must be treated as a transmission line with characteristic impedance Z0, phase constant β, length l, propagation delay, conductor and dielectric loss, and frequency-dependent coupling.
The lossless line equations used for a section are:
V1 = cos(βl)V2 + jZ0sin(βl)I2
I1 = j[sin(βl)/Z0]V2 + cos(βl)I2
These equations, combined with the source and load equations, predict output current and delivered power more accurately than a simple turns-ratio model. The high-frequency treatment is developed in All About Circuits’ Ruthroff analysis.
The basic 1:4 design
Ratio and line impedance
For an ideal voltage ratio n, the impedance ratio is n2. Thus a 1:2 voltage ratio gives 1:4 impedance transformation. For a source resistance RS and load resistance RL, select the first-pass line impedance as:
Z0 ≈ √(RSRL)
For 50 Ω to 200 Ω, Z0 = √(50 × 200) = 100 Ω. This is a starting value, not a guaranteed optimum: winding geometry, launches, package parasitics and the actual source and load may require adjustment.
Sign conventions and port definition
Draw the winding or coupled-line schematic with dot markings, current arrows and explicit grounds before calculating. The same conductors can produce an unun, a voltage balun or a center-tapped balanced output depending on how they are connected. Verify the intended polarity with a low-power network-analyzer measurement rather than relying on wire color.
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Why bandwidth falls at the high-frequency end
The basic Ruthroff circuit combines a direct signal with a delayed signal. Their phase difference grows with frequency as the line’s electrical length increases:
θ = βl = 2πl/λg
Here λg is the guided wavelength, not free-space wavelength. As θ grows, voltage addition is no longer exact. The usual symptoms are increasing insertion loss, amplitude ripple, phase error, poorer return loss and, in a balun, degraded balance or common-mode rejection. A severe response null can occur when the line becomes an appreciable fraction of a wavelength.
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This is why a transformer can show the correct low-frequency 1:4 ratio yet fail a broadband specification. The published analysis gives approximately 1 MHz to at least 500 MHz as an example range for equal-delay structures at particular impedance levels and implementations; it is not a universal rating.
Equal-delay improvement
An equal-delay Ruthroff transformer adds a compensating transmission-line path between the relevant nodes. The added path is chosen so the important voltage contributions have approximately the same electrical delay before they combine. This reduces phase error and can extend the useful upper-frequency limit.
Designing the compensating path
- Identify the direct and delayed signal paths in the schematic.
- Estimate the main line’s propagation delay or electrical length.
- Add a path with approximately equal electrical delay; match electrical length, not merely physical length.
- Choose its characteristic impedance deliberately and account for coupling to adjacent conductors.
- Include bends, vias, connectors, winding transitions and dielectric changes in the model.
- Simulate or measure amplitude and phase through the full band, then trim length or impedance.
A line routed through a different dielectric has a different propagation velocity, so two traces of equal physical length can still have unequal delay. The extra line is a phase-compensation element, not simply an extra turn.
Extending the ratio
Additional transmission-line sections extend the voltage-addition mechanism. In the idealized structures described in the published analysis:
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| Sections | Ideal voltage ratio | Ideal impedance ratio |
|---|---|---|
| One | 1:2 | 1:4 |
| Two | 1:3 | 1:9 |
| Three | 1:4 | 1:16 |
For 1:9, Rratio = 32; for 1:16, it is 42. Real structures depart from these values as each line adds loss, delay error, parasitic capacitance and layout sensitivity. Higher ratios also increase voltage stress and make symmetry harder to preserve.
A complete design workflow
1. Specify the system
- Source and load impedances and required ratio.
- Frequency range and limits for return loss, insertion loss, amplitude and phase imbalance.
- RF power, peak voltage, DC current, duty cycle and temperature range.
- Balanced or unbalanced ports, isolation requirement and mechanical or PCB constraints.
2. Select the medium
Options include twisted bifilar wire on ferrite, coax wound through a core, twin-lead, parallel-wire line, stripline, microstrip, broadside-coupled PCB traces and integrated planar lines. Frequency, power, voltage, balance, size and manufacturability determine the choice. The University of Surrey thesis record discusses multilayer implementations, balanced lines, parasitic common-mode currents and de-embedding.
3. Check electrical length
Estimate θ using the guided wavelength or measured delay. Keep the line electrically short enough for the uncompensated topology, or use equal-delay compensation. A full electromagnetic or RF-circuit model is preferable to a lumped approximation.
4. Check low-frequency inductance
At the low end, winding reactance must dominate the port impedance:
XL = 2πfL
Insufficient inductance causes low-frequency droop, loss and poor return loss. More turns raise inductance but also increase interwinding capacitance, leakage inductance, delay, loss and resonance risk. Broadband design is a compromise between the low and high ends.
5. Select and stress the core
Ferrite improves flux linkage and allows useful inductance with fewer turns, but permeability, loss and saturation vary with frequency, temperature, RF voltage, RF current, DC bias and waveform crest factor. DC current can drive the core toward saturation, changing insertion loss and bandwidth. Check the core manufacturer’s material data; the Fair-Rite 17th Edition Catalog provides core dimensions, materials and impedance data but does not constitute a finished transformer design.
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Power, DC and construction limits
- Specify DC current separately from RF current; DC bias can reduce bandwidth and increase distortion.
- Check core temperature, copper loss, wire insulation, current density and connector heating under mismatch.
- For high voltage or pulsed service, check peak voltage, arcing and corona rather than average power alone.
- Keep loop area small and conductors symmetrical to limit leakage and common-mode current.
Ferrite is not automatically a high-power solution: larger cores, different materials, heavier conductors or a different topology may be required.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Measurement and verification
Minimum test set
- Calibrated VNA measurements of S11, S22, S21 and, where relevant, S12.
- Amplitude and phase balance for balanced outputs.
- Common-mode conversion or rejection.
- DC resistance, insulation resistance and temperature rise under power.
Fixture discipline
Fixture mismatch, connector repeatability, cable phase, port-extension errors, radiation, ground-current paths and PCB launch discontinuities can dominate the result. Balanced ports require an appropriate multiport calibration or balun fixture and, for planar designs, de-embedding. The Surrey thesis record describes these calibration and measurement issues.
Failure signatures
| Observed symptom | Likely cause | First corrective action |
|---|---|---|
| Low-frequency roll-off | Insufficient inductance or unsuitable core | Increase effective inductance, change core or lower the minimum frequency |
| High-frequency roll-off | Excessive delay, capacitance or loss | Shorten or re-route the line, reduce parasitics or add equal-delay compensation |
| Narrow resonance | Leakage inductance and distributed capacitance | Change winding geometry or damp the resonance |
| Poor return loss | Incorrect Z0, mismatch or launch discontinuity | Recalculate the geometric-mean value and inspect the fixture |
| Amplitude or phase imbalance | Unequal electrical paths or coupling | Equalize paths and improve physical symmetry |
| Heating or compression | Core loss, copper loss, saturation or common-mode current | Reduce power, enlarge or change the core, or change topology |
Ruthroff or Guanella?
| Criterion | Ruthroff | Guanella |
|---|---|---|
| Main mechanism | Voltage addition in a bootstrapped line | Parallel-series transmission-line sections |
| Typical strength | Compact, simple, naturally extendable ratios | Good delay symmetry, balance and broadband current-balun behavior |
| Main concern | Phase error from unequal propagation delay | More conductors, core usage or layout area may be needed |
| Best fit | Compact 1:4, 1:9 or 1:16 voltage transformation when delay is controlled | Very wide bandwidth, balanced outputs and common-mode control |
These are tendencies, not laws. Choose based on bandwidth, balance, power, ratio, current handling, size and implementation. A Guanella is often preferable when balanced performance is the primary specification; a Ruthroff is attractive when compact voltage transformation and simple construction matter.
When a catalog transformer is the better answer
Buy a qualified part when its ratio, frequency range, package, power and balance specifications already match the system. Representative Mini-Circuits options are:
| Part | Stated range | Use case and qualification |
|---|---|---|
| TC4-1TX+ | 0.5–300 MHz | HF to low-VHF 1:4 applications; observed stock and pricing change over time |
| TC4-14+ | 200–1400 MHz | Applications beginning in the hundreds of megahertz; verify low-frequency limit |
| TC4-19G2+ | 10–1900 MHz | Broad catalog coverage; catalog bandwidth does not guarantee custom balance or phase behavior |
| TMO-4-1+ | 0.2–350 MHz | Metal-case or robust packaging; availability and price must be checked before purchase |
Observed prices and stock for these products were snapshot values from August 16, 2026 and are not specifications. A catalog 1:4 part is not automatically a substitute for a custom equal-delay network: verify insertion loss, return loss, phase and amplitude balance, DC-current capability and power in the actual circuit.
Planar and integrated implementations
Planar Ruthroff structures can reduce bulk and suit microwave or IC processes. A 2024 GaAs p-HEMT implementation for an 8–30 GHz passive mixer used shunt capacitors, parallel coupled lines and compensation to improve isolation and amplitude/phase balance. That application-specific result, reported in Micromachines and indexed by PubMed, is not a universal operating range for ferrite-wound transformers.
Quick Recap
Final design checklist
- Define source, load, ratio, frequency and acceptance limits.
- Calculate the first-pass Z0 from the geometric mean.
- Choose a line medium and core appropriate to power, voltage and DC bias.
- Estimate guided delay and decide whether equal-delay compensation is required.
- Check low-frequency inductive reactance and high-frequency parasitics.
- Keep balanced paths electrically—not just physically—symmetric.
- Measure calibrated S-parameters, balance, common-mode behavior and thermal performance.
- Use a Guanella or qualified catalog part when it meets the specification with less risk.
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
