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Analog Devices (ADI) and TSMC announced a jointly developed 0.18-micron (180-nm), 5-volt process platform for precision analog integrated circuits on 20 June 2012. The announcement described it as TSMC’s 0.18-micron BCD process: a specialty analog and mixed-signal manufacturing collaboration, not a new standalone chip or a claim about competing in the leading-edge logic-node race.

What ADI and TSMC announced

The companies said they had collaborated on a process platform intended to help make precision analog ICs. They described it as 0.18 micron, equivalent in scale to 180 nm, and 5 volt, and identified it as TSMC’s 0.18-micron BCD process. The release also characterized the platform as supporting a range of operating voltages and as cost-effective, compact, and energy-efficient; those descriptions were not accompanied by quantified comparisons.

The announcement followed a longer relationship between the companies. Rick Cassidy, then president of TSMC North America, said: “ADI has worked with TSMC since the 0.6-micron and 0.35-micron analog processes.” The title and role reflect the 2012 announcement, not a present-day position.

Performance improvements the companies reported

ADI and TSMC attributed four improvements to the process in their 2012 announcement:

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Noise Improved by an order of magnitude
Standby leakage current Reduced by 70 percent
Linearity Improved by 50 percent
Capacitor and resistor matching Improved by 50 percent

These are claims from the joint company release, not independently reproduced results. The announcement does not give test conditions, define the comparison baseline, or provide independent validation, so the figures should not be read as guaranteed gains for a particular design or as evidence of specific system-level improvements.

Applications and ADI products named in the release

The platform was presented as suitable for several analog and mixed-signal applications:

  • Analog-to-digital and digital-to-analog converters
  • Power-management devices
  • Audio codecs

The release situated these applications in consumer, communications, computer, industrial, and automotive equipment. It also named recently introduced ADI products developed with the platform: isolated CAN transceivers, a HART modem IC, an ECG analog front end, digital potentiometers, and an audio codec. These are examples cited in 2012, not an exhaustive list of products.

David Robertson, then ADI’s vice president of Analog Technology, said: “The combination of an optimized process along with circuit and architecture innovation is key for our high-performance converter and linear products.” His comment emphasized that process technology is one part of product performance, alongside circuit and architecture design.

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What later manufacturing notices do—and do not—establish

ADI’s 1 February 2024 product change notice, PCN 24_0009, says the company was adding its Beaverton, Oregon site as an alternate wafer-fab site to TSMC Taiwan for a 0.18um mixed-signal CMOS process. The notice gave 5 May 2024 as the change’s effectivity date, said the change was intended to support manufacturing agility and continuity of supply, and stated there would be no impact to form, fit, function, or reliability. It lists affected ADI models and says manufacturing location is tracked internally via device marking. This is later manufacturing context; it does not establish that every listed device uses the precise configuration described in 2012, or that the 2012 platform remains unchanged.

ADI separately announced a long-term wafer-capacity arrangement on 22 February 2024 through JASM, TSMC’s majority-owned subsidiary in Kumamoto, Japan. That announcement concerns fine-pitch technology nodes and applications including wireless battery-management systems and GMSL. It does not identify the 2012 0.18-micron analog platform as part of the arrangement.

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Is the 180-nm platform available today?

The available announcements do not establish whether the exact 2012 platform is currently offered, available to third parties, or unchanged. Nor do they provide current design rules, qualification details, or access terms. The 2024 PCN documents a particular ADI manufacturing-site change for a 0.18um mixed-signal process, but that is not enough to determine the present status of the earlier platform.

For engineers evaluating a process today, the 2012 figures alone are not a basis for comparison. A meaningful assessment would require matched information about operating voltage, noise measurement and baseline, leakage test conditions, linearity definition, capacitor and resistor matching methods, design rules, qualification, and availability.

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