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Microprocessor debugging shifted from replacing the CPU with a costly external emulator to accessing debug logic built into the chip. Faster clocks, caches and integrated peripherals made external observation less useful, while JTAG, compressed trace and ARM CoreSight provided ways to reach and record activity inside increasingly complex systems.
How debugging worked before JTAG
In the 1970s and 1980s, a common development setup combined a CPU with ROM or EPROM, RAM and separate peripherals. Developers compiled and linked their program into a HEX image, programmed a removable EPROM, installed it in the board and powered the system up. When something went wrong, they might inspect code, watch LEDs, connect a logic analyser or use a serial monitor running on the target.
A serial monitor could let a developer single-step instructions and inspect registers and memory, but it depended on the target running enough code to communicate. The Embedded.com history describes these manual and ROM-based workflows, including the repeated erase, program and reinstall cycle for EPROMs.
In-circuit emulators and bond-out CPUs
Teams with more budget could use an in-circuit emulator (ICE): electronics that stood in for the target CPU while the developer worked on the board. Some systems used a bond-out version of the processor, exposing internal signals unavailable on an ordinary production part. That visibility enabled complex breakpoints and trace; emulation RAM could also stand in for the target EPROM during development. These systems were physically large and, according to the Embedded.com history, cost many thousands of dollars.
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Why ICE and external trace became harder to use
From the 1980s onward, CPUs integrated more functions and ran at higher clock rates. An external emulator had to keep pace electrically, and the cabling and control needed to observe fast signals became more difficult and expensive. Manufacturers were also less willing to produce bond-out parts. An Embedded.com history published in 2017 gives one concrete price point: an ICE for an Intel 80186 could be acquired for less than $10,000.
External bus trace also lost some of its usefulness as caches and integrated peripherals became more important. A trace of activity visible at external pins could miss execution and accesses happening internally. The trade-off shifted: external trace could show bus activity directly, while on-chip debug could observe internal signals at core speed but needed a way to transport and store the captured information.
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When JTAG became a route to debugging
The Joint Test Action Group developed boundary-scan techniques between 1986 and 1990. IEEE 1149.1 standardized a test access port (TAP) and boundary-scan architecture, primarily to help test connections between integrated circuits on an assembled board. The standard’s scope is broader than board testing: IEEE 1149.1-2013 also describes observing, modifying or loading data inside an IC during test, programming, configuration or debug.
Vendors subsequently used JTAG as an access route to on-chip debug logic. JTAG did not make every processor’s debug features identical: the access standard and the vendor’s debug implementation are distinct. In the 1990s, proprietary Background Debug Mode (BDM) and JTAG-accessed on-chip debug offered alternatives to relying on an external emulator for visibility into a processor.
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ICE, BDM and JTAG compared
| Approach | What it provides | Main trade-off |
|---|---|---|
| In-circuit emulator (ICE) | Replaces or emulates the target CPU; bond-out variants can expose internal signals for breakpoints and trace. | High visibility, but physically large and expensive; faster clocks made emulator connections more difficult. |
| Background Debug Mode (BDM) | A proprietary on-chip debug access method. | Provides an alternative to CPU-replacement emulation, but implementation depends on the vendor; the historical source does not establish a universal BDM feature set. |
| JTAG | A standardized TAP and boundary-scan approach that vendors also used to reach on-chip debug components. | Creates a standardized access path, but the debug capabilities behind it remain dependent on the chip and its vendor implementation. |
How compressed trace and ETB made execution history practical
In the early 2000s, trace systems increasingly represented execution paths as compressed data rather than sending every instruction event as a full record. With the program image, a debugger could reconstruct sequential portions of execution from that compressed stream, reducing the bandwidth needed to transport trace.
ARM’s Embedded Trace Buffer (ETB), accessed through JTAG, put a relatively small trace buffer on the chip. Instead of requiring a very fast external trace port to capture activity, a system could store trace locally and retrieve it through the debug access path. That made execution-history capture more practical when external pins and bandwidth were limited.
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How ARM CoreSight handled multi-core power management
As ARM-based systems added multiple cores and power management, a serial JTAG chain created a problem: a powered-down core could disappear from the chain, even though JTAG does not support changing the scan chain that way. ARM CoreSight addressed this by presenting one JTAG-based debug access port connected to multiple memory-mapped debug components.
With that arrangement, individual cores and components could power down without requiring the scan chain itself to change. It separated the external access point from the many debug blocks inside the system-on-chip (SoC), a more suitable arrangement for multi-core designs than treating each core as a link that must remain active in one serial chain.
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What changed from 2010 to 2016
As 64-bit processors and Linux- and Android-based systems grew more capable, debug increasingly included capture and analysis on the target device. Kernel drivers exposed CoreSight components, and Linux’s perf subsystem enabled on-target trace capture and analysis.
ARM Embedded Logic Analyser features added complex on-chip triggers and trace over internal SoC signals. These capabilities brought back some of the internal visibility associated with early bond-out ICEs, but through integrated instrumentation rather than a CPU-replacement emulator.
What hardware is needed for JTAG or SWD debugging?
The required connection depends on the target device: JTAG and Serial Wire Debug (SWD) are not interchangeable assumptions for every chip. Microchip’s Atmel-ICE guide says SAM devices support SWD and that some also support JTAG. For those devices, the guide describes JTAG as a four-wire IEEE 1149.1 TAP and documents Arm CoreSight-compliant on-chip debug components. It separately identifies AVR UC3 as using a Nexus 2.0-compliant debug system with hardware breakpoints, watchpoints and real-time program-counter, data and process trace.
- Check the target device’s documentation to determine whether it supports JTAG, SWD or another debug interface, and which on-chip debug architecture it implements.
- Use a probe that supports that interface and the target’s debug implementation, with a physical connection matching the board’s debug header or pads.
- Use host-side debugger software that supports both the probe and target. JTAG or SWD provides access; it does not by itself define the target’s available breakpoints, watchpoints or trace features.
The Atmel-ICE guide is a concrete example, not a universal compatibility list: its interface and component details apply to the device families it documents.
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