IBM’s June 2017 announcement described a research process for building silicon nanosheet transistors intended to enable 5 nm chips. IBM said the approach could fit 30 billion switches on a fingernail-sized chip; it was a research milestone, not a retail processor launch.
What IBM announced in 2017
IBM said an alliance led by the company had developed an “industry-first process” for building silicon nanosheet transistors. The work involved IBM, GLOBALFOUNDRIES, Samsung, equipment suppliers and the IBM-led research alliance at the SUNY Polytechnic Institute NanoTech Complex in Albany, New York. IBM’s stated density potential was 30 billion switches on a fingernail-sized chip. IBM’s announcement also described an earlier 7 nm test-node chip from the alliance as having 20 billion transistors.
These were company-reported research claims, not independently validated specifications for a product. The announcement did not name a consumer processor or device available to buy.
How nanosheet transistors differ from FinFETs
A transistor controls the flow of electrical current through a channel. In the FinFET design IBM described as the industry blueprint through the 7 nm generation, that channel is fin-shaped. IBM’s explanation was that merely shrinking the spaces between fins does not provide additional current flow.
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IBM’s alternative stacked thin silicon sheets to form the channel. The sheet width could be adjusted, giving designers another way to tune current, power use and performance for particular circuits. IBM later characterized its approach as gate-all-around (GAA) nanosheets: the gate surrounds the channel, improving electrostatic control, while variable sheet widths and channel-thickness control offer design flexibility. These are IBM’s descriptions of the architecture, not a third-party assessment. IBM Research’s technical account discusses that rationale.
What the 30-billion figure does—and does not—tell you
The 30 billion figure was IBM’s projected transistor density for a chip described as fingernail-sized. It conveys the potential number of switching devices in a compact area; it does not specify a retail chip’s performance, power consumption or usefulness for a particular workload. The announcement’s shorthand term “switches” refers to transistors.
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IBM also projected a 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance, compared with then-leading 10 nm technology. Both percentages came from IBM’s 2017 announcement and its stated comparison basis. They should not be read as measurements of a product available to consumers.
Does “5 nm” mean every feature is five nanometers wide?
No. “5 nm” is a process-generation label, not a promise that every transistor or physical feature measures exactly five nanometers. In a 2021 explanation of node naming, IBM said labels such as 10 nm, 7 nm, 5 nm and 2 nm refer to chip generations made using particular manufacturing processes. IBM also noted that its 2 nm label did not correspond to half-pitch of contacted metal wires under the traditional definition. IBM’s node-label explanation provides that context.
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How the 2017 result relates to later IBM milestones
IBM continued to report nanosheet research after the 2017 announcement, but later figures describe separate milestones and comparison baselines:
| Milestone | Structure and density claim | Performance or power comparison | What the claim represents |
|---|---|---|---|
| 2017, 5 nm | Silicon nanosheets; potential for 30 billion switches on a fingernail-sized chip, according to IBM. | IBM projected 40% more performance at fixed power, or 75% less power at matched performance, versus then-leading 10 nm technology. | IBM’s research-process announcement, not a retail product specification. |
| 2019, 5 nm research account | IBM described gate-all-around stacked nanosheets, including variable sheet widths and channel-thickness control. | IBM Research reported more than 25% performance enhancement at the same power, or more than 50% power savings at the same performance, compared with then-available 7 nm FinFET foundry technology. | A separate IBM Research comparison with a different baseline; it is not directly comparable to the 2017 10 nm comparison. |
| 2021, 2 nm | IBM reported up to 50 billion transistors on a fingernail-sized chip. | Not stated in the cited source as a comparison to the 2017 5 nm figures. | A later research milestone, not the 2017 5 nm demonstration. IBM’s 2021 announcement describes it. |
The 2019 figures are from IBM Research’s 2019 account. The percentages use different comparison technologies, so they should not be lined up as if they came from one experiment. IBM’s 2021 report of up to 50 billion transistors likewise describes a different generation and milestone.
Was IBM’s 5 nm chip available to buy?
No consumer processor or device was identified for sale in the 2017 announcement. It described a research process demonstration aimed at enabling 5 nm chips, not a commercial product launch. IBM’s 2021 account of its 2 nm research milestone said manufacturing of 2 nm devices was still several years away at that time. That was a historical statement and does not establish current manufacturing plans. IBM’s 2021 explanation gives that qualification.
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