Goldmont Plus is the low-power Intel Atom microarchitecture used in Gemini Lake processors. Its defining change from Goldmont is in the back end: Intel widened allocation and retirement to four-wide, but kept fetch and decode three-wide. That makes it inaccurate to describe Goldmont Plus as a four-wide decoder—and the design changes alone do not establish how much faster any particular application will run.
Which processors use Goldmont Plus?
Linux’s x86 family mapping identifies processor family 6, model 0x7A as Goldmont Plus and associates it with Gemini Lake. Intel’s Gemini Lake platform page lists Pentium Silver N5xxx and J5xxx, and Celeron N4xxx and J4xxx processor families. Those family names identify the platform’s processor lines; a specific product’s exact CPU should be checked in its specifications.
Linux’s mapping is available in the x86 family header. Intel’s platform page establishes the family naming, not present-day retail availability.
What changed from Goldmont?
Intel’s Optimization Reference Manual, section 6.7, describes the core as widening its back-end pipeline “to 4-wide allocation to 4-wide retire, while maintaining 3-wide fetch and decode.” Allocation and retirement are back-end stages; they do not mean the processor fetches or decodes four instructions per cycle.
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The front-end comparison in Intel’s table 6-8 lists three decoders and maximum decoder throughput of 20 bytes per cycle for both Goldmont Plus and Goldmont. The manual also lists a larger shared second-level pre-decode cache: 64 KB for Goldmont Plus, compared with 16 KB for Goldmont.
How do the execution and memory resources differ?
Intel documents several changes intended to support instruction scheduling and execution. They describe the design, not independently measured gains in a particular workload.
Rank #2
- 2 Cores /2 threads
- Base frequency 3.1 GHz
- Compatible with Intel 300 Series chipset based motherboards
- Thermal solution included
- Out-of-order execution: larger reservation stations and reorder-buffer entries provide a larger window of instructions for the core to consider.
- Integer and branch work: a wider integer execution unit and a dedicated JEU (Jump Execution Unit) port are listed for branch redirection.
- Floating-point division: Intel lists a radix-1024 divider for scalar and packed single-, double-, and extended-precision operations.
- Encryption: Intel lists improved AES-NI throughput and latency.
- Loads and stores: larger load/store buffers and improved store-to-load forwarding for register-sourced store data are documented.
- Address translation: Intel lists a shared second-level instruction/data TLB and paging-cache enhancements.
For system design, Intel describes a modular arrangement in which four cores share up to 4 MB of L2 cache. “Up to” matters: the manual’s stated maximum should not be read as a cache capacity guaranteed on every Gemini Lake processor.
Did every listed metric improve?
No. The manual’s comparison shows continuity in the front end and a longer listed branch-mispredict penalty for Goldmont Plus. Table 6-8 gives 13 cycles for Goldmont Plus, or 12 cycles for certain conditional branches, versus 12 cycles for Goldmont. This is a specific manual comparison, not a prediction that every branch-heavy program will be slower.
Rank #3
- 3.6GHz Operating Frequency, LGA1200 Socket
- Rocket Lake Series
- Intel Boxed Desktop CPU
- Core i7-11700KF with 16MB cache
- 8 core /16 threads
The combination of a larger pre-decode cache, wider back-end stages, and changed execution and buffering resources is a meaningful architectural update. But pipeline specifications cannot by themselves quantify application performance. The selected technical documentation does not provide controlled benchmarks establishing a general speedup over Goldmont.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What should a buyer infer from the architecture?
Goldmont Plus tells you which core design sits behind a Gemini Lake CPU; it does not rank complete computers. If comparing systems, verify each model’s exact processor, memory, storage, thermal design, ports, price, and availability. Two systems with CPUs from the same family can still differ substantially in configuration and implementation.
For a technical comparison of the cores, the most informative points are the four-wide allocation and retirement versus three-wide fetch and decode, the pre-decode cache increase, branch-mispredict figures, execution resources, and memory-side buffers and TLB organization. Treat Intel’s listed changes as architectural specifications rather than benchmark results.
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