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Ambiq’s August 2025 announcement described two ways to run edge-AI models on its Apollo microcontrollers: HeliosRT, an interpreter-style runtime derived from TensorFlow Lite for Microcontrollers (TFLM), and HeliosAOT, which compiles a model into C code for inclusion in firmware. The choice is a trade-off between a familiar model workflow and generated code with less interpreter overhead—not a proven universal win for either option. Separately, Ambiq completed an upsized IPO in July 2025, raising $110.4 million in gross proceeds before expenses.
What are HeliosRT and HeliosAOT?
In an August 1, 2025 Embedded article, Ambiq presented HeliosRT and HeliosAOT as software approaches for deploying AI models on resource-constrained embedded hardware, particularly its Apollo family. They differ mainly in when model operations are resolved: while the firmware runs, or before the firmware is built.
HeliosRT: an interpreter derived from TFLM
HeliosRT is described as an Apollo-optimized fork of TensorFlow Lite for Microcontrollers. It keeps an interpreter-style workflow, with Ambiq-optimized kernels for operations commonly used in edge-AI models. That approach may suit a team seeking to retain a familiar TFLM-oriented model workflow rather than compile each model into generated C code.
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Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Ambiq vice president of AI Carlos Morales told Embedded, “We’ve developed a range of optimized kernels to handle operations commonly found in edge AI models.” The article also says specialized lookup-table optimizations can improve model performance by 10–30%. Both the range and the kernel-coverage description are Ambiq claims reported in the article; it does not supply an independent audit of operator coverage or a complete benchmark methodology.
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HeliosAOT: model operations compiled into firmware
HeliosAOT takes a different route: it converts a model ahead of time into C code that can be built into firmware. According to the article, resolving operators and metadata at compile time removes interpreter scheduling and lookup work during inference, and lets the build include only the kernels the model needs. In exchange, the generated code must be integrated into the firmware build.
Ambiq says this approach can reduce memory footprint by 15–50% compared with interpreter-based deployment. Morales also described a HeartKit example in which changing only the runtime delivered “almost 5x better performance without modifying the model.” These are reported company figures, not independently established results in the article; the source does not provide a complete side-by-side test matrix or enough test conditions to generalize the figures to other models and devices.
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How should developers choose between the runtimes?
The article offers design descriptions and company-reported figures, not a universal ranking. A useful decision should be based on the target Apollo device and the actual model, conversion workflow, and firmware constraints.
| Consideration | HeliosRT | HeliosAOT |
|---|---|---|
| Execution | Interpreter-style model execution; described as a TFLM fork. | Model compiled ahead of time to C code and incorporated into firmware. |
| Workflow | Retains a familiar TensorFlow/TFLM-oriented approach while using Apollo-optimized kernels. | Resolves operators and metadata at compile time; includes the kernels required by the model. |
| Potential fit | Teams that value the interpreter workflow or are not ready to deploy generated model code. | Teams prepared to integrate compiled model code and configure memory use. |
| Trade-off | Retains interpreter execution; the article does not provide an independent audit of kernel coverage. | Requires compilation and firmware integration; layer placement and memory planning may need configuration. |
Before choosing, compare both routes on the intended device and model. Measure inference latency, peak RAM and firmware size; confirm that the needed operators are supported; and check how each route fits the existing model-conversion and build process. If the application has specific memory-placement requirements, evaluate those as well. The article does not establish that either runtime is always faster or smaller.
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- Dual-core processor: The ESP32 module is based on the powerful ESP32-S3-WROOM N16R8 module and is equipped with a dual-core 32-bit LX7 processor. Its excellent AI computing performance, real-time processing capabilities, and low power consumption make it ideal for image recognition, edge AI, and complex IoT applications
- Integrated 2-megapixel OV3660 camera: Built-in OV3660 camera to capture clear images and stream video in real time. Perfect for smart surveillance, face recognition, and AI-based computer vision projects. It is the preferred solution for DIY makers and professionals to build camera-enabled IoT systems
- Dual Type-C ports for OTG and serial debugging: Designed with two USB Type-C interfaces - one supports USB OTG for host/device functions, and the other provides TTL serial for easy programming and debugging
- Shared antenna: Supports IEEE 802.11b/g/n Wi-Fi (2.4GHz) and Bluetooth 5 (LE and Mesh), using shared antennas to optimize wireless performance. Enhanced 2 Mbps PHY and long-distance communication (Coded PHY) ensure stable multitasking in harsh environments
- Multi-scenario applications: The ESP32 S3 development board maintains high stability even at high temperatures, making it ideal for industrial environments, educational purposes, and AI-driven projects. It is a versatile choice for robots, smart devices, and machine vision in lab or field applications
What memory controls does HeliosAOT describe?
Ambiq principal AI engineer Dr. Adam Page described planned scratch-buffer reuse and configurable allocation across TCM, SRAM, and MRAM. Developers can use a YAML file to specify where layers go; Page said the generated code mirrors the network structure. These are implementation options described for HeliosAOT in the Embedded article, not evidence that every Apollo device exposes all three memory types or provides identical capacity and performance.
What did “goes public” mean for Ambiq?
Ambiq’s IPO was a separate corporate event from the runtime announcement. The company’s July 31, 2025 closing announcement says it sold 4.6 million shares at $24 each, for $110.4 million in gross proceeds before expenses. The shares began trading on the New York Stock Exchange under the ticker AMBQ on July 30, 2025.
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The $110.4 million amount is the closed, upsized offering figure. Ambiq’s earlier July 29, 2025 pricing announcement gave expected gross proceeds of $96 million. These figures refer to different stages of the offering, so the earlier estimate should not be confused with the final proceeds at closing. Ambiq’s annual report filed with the SEC also identifies the IPO closing date and ticker.
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What is established about availability today?
A later Ambiq announcement dated September 23, 2025 described HeliaRT beta integration for Apollo510 and Apollo510B in neuralSPOT SDK V1.2.0, and an ahead-of-time HeliaAOT integration as experimental. It is useful as historical product context, but does not establish the October 2026 release status, licensing, supported-chip matrix, or benchmark performance of the HeliosRT and HeliosAOT solutions discussed in the August article. Ambiq’s announcement is available at neuralSPOT SDK V1.2.0 with Helia integration.
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