Cadence announced and taped out an Arm-based system chiplet on November 19, 2024. Rather than acting only as a compute or accelerator die, it is designed to manage resources across a multi-chiplet system-on-chip (SoC). Cadence presented it as part of a broader collaboration with Arm, not as proof of a retail product or a deployed system.
What makes it a system chiplet?
A chiplet is a functional die intended to work alongside other dies in a larger package. Cadence’s design is distinctive in its stated role: managing system-level resources and functionality across the overall multi-chiplet SoC, rather than providing only one application-specific function such as computation or acceleration. The announcement describes the design and its tapeout, but does not report customer deployments or subsequent silicon results. Cadence’s November 19, 2024 announcement
What Cadence says the chiplet contains
Cadence describes processors, system IP, and memory IP in one package. The named components indicate how the chiplet is meant to coordinate and connect a larger design:
- System processor: a processing element for system-level functions.
- Safety management processor: a separate named element for safety-management functions.
- Cadence controllers and Janus NoC technology: controller IP and network-on-chip technology, which Cadence identifies among the design’s system components.
- LPDDR5 and UCIe PHY IP: physical-layer IP for memory and chiplet connectivity, respectively.
The announcement does not detail the implementation, workload allocation, or safety certification of these components. Their inclusion should not be read as proof of any particular system capability or certification.
Do these 3 things before closing this tab:
1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitches#1 Best Overall
- High-performance foundation line, ARM Cortex-M4 core with DSP and FPU, 512 Kbytes Flash, 180 MHz CPU, ART Accelerator, Dual QSPI
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
How UCIe and Arm CSA fit
Cadence says the chiplet uses UCIe to connect chiplets and complies with Arm’s Chiplet System Architecture (CSA). UCIe is the interconnect interface cited for die-to-die connections; CSA is the architecture framework cited by Cadence. Together, they describe the standards and framework informing this design. They do not guarantee that every UCIe- or CSA-based component will interoperate automatically: compatibility depends on the specific implementations and the rest of the system.
What the bandwidth figures do—and do not—show
Cadence reported these peak figures for its IP in the 2024 announcement:
Rank #2
- Ultra-low-power with FPU ARM Cortex-M4 MCU 80 MHz with 1 Mbyte Flash, LCD, USB OTG, DFSDM
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
| IP | Cadence-reported figure | How to interpret it |
|---|---|---|
| UCIe | Up to 64 GB/s peak bandwidth | A peak IP figure reported by Cadence, not an independently verified system benchmark. |
| LPDDR5 | Up to 32 GB/s peak memory bandwidth | A peak IP figure reported by Cadence, not evidence of sustained application performance. |
These are “up to” peak figures, not measurements of a complete system running real workloads. The announcement supplies no independent benchmark results, operating conditions, or application-level performance data.
How it could change SoC design
Moving system-management functions into a chiplet could let designers organize a multi-die SoC differently from a single monolithic die. Cadence frames reduced design complexity, IP reuse, and faster time to market as goals or potential benefits of the design. Those are intended benefits, not measured customer outcomes in the announcement.
Rank #3
Evaluating the approach requires more than the chiplet’s stated bandwidth figures. Designers would also need to consider:
- Modularity and reuse: whether system functions can be reused across designs without excessive redesign.
- Interoperability: whether the chiplet’s interface and architecture work with the particular dies and system implementation.
- Packaging and integration: the engineering required to connect and validate multiple dies.
- System-level performance: measured results under relevant workloads, which the announcement does not provide.
The release names no competing products and provides no monolithic-SoC comparison, so it does not establish that this design outperforms a particular alternative.
Rank #4
- Mainstream Mixed signals MCUs ARM Cortex-M4 core with DSP and FPU, 512 Kbytes Flash, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB.
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
What the Arm collaboration establishes
Cadence says it collaborated with Arm and connects the chiplet to a broader effort to deliver a chiplet-based reference design and software development platform. That describes the announced direction of the collaboration; it does not establish that the system chiplet is a generally available product, that a reference platform has shipped, or that later deployment results have been demonstrated.
Quick Recap
Best Value
- STM32F103C8T6 ARM STM32 minimum system development module.
- ST-Link V2 support the full range of STM32 SWD interface debugging, simple interface (including power supply), 4 line speed, stable work.
- Use the current smart phones of Mirco USB interface, easy to use, USB communication and power supply can be done.
- The board lead to all the I/O resources.Download with SWD debug interface, which requires a minimum of 3 wires to complete debug a download task
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
