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Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →In August 2000, EDN reported that NEC and Toshiba had begun retooling DRAM fabs for 0.18-micron line widths as they prepared for volume production of 256-megabit memory chips. The report describes two companies moving their manufacturing processes toward a denser DRAM generation—not a joint product launch—and says their capacity and product strategies differed.
What the 0.18-micron report says
EDN’s 15 August 2000 report states that NEC and Toshiba had started retooling their DRAM fabrication plants to produce devices with 0.18-micron line widths, in preparation for 256-Mbit DRAM volume production. Here, 0.18 micron is equivalent to 180 nanometres. The figure describes the process rules or line widths cited in the period report; by itself, it does not establish that every device feature was 180 nanometres, specify gate length, or mean the same thing as a modern process-node label.
The account is a contemporaneous trade report, not a retrieved joint announcement from NEC and Toshiba. EDN also described different product-mix plans for the companies, so “intro” is best understood as a reported fab and process transition rather than a shared chip launch. Read EDN’s report.
How NEC and Toshiba planned to use the transition
| Company | Product and capacity strategy reported by EDN | Intended positioning |
|---|---|---|
| NEC | Preparing 256-Mbit chips while planning to double 128-Mbit SDRAM capacity, increase wafer output, and reduce 64-Mbit SDRAM production. | EDN said NEC had begun applying 0.18-micron rules to 288-Mbit Rambus DRAMs. It reported that NEC expected these products to target high-end servers and workstations, with desktop systems a possible later market. |
| Toshiba | Winding down 128-Mbit synchronous DRAM production in favor of Rambus and 256-Mbit devices, while limiting new DRAM wafer starts. | The report framed Toshiba’s mix around higher-density and Rambus products; it did not describe NEC’s planned increase in 128-Mbit SDRAM capacity as Toshiba’s strategy. |
These are plans and expectations as EDN reported them in August 2000, not proof that every target was subsequently achieved. The market progression for NEC’s Rambus DRAMs was an expected path, not a confirmed later outcome.
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Related 0.18-micron activity—and what it does not prove
Other period announcements show that 0.18-micron manufacturing was part of broader semiconductor development, but they concern different products or programs and do not independently confirm the specific DRAM-fab transition EDN described.
- Toshiba system LSIs: In April 2000, Toshiba announced a planned 30-billion-yen investment in its Oita plant for advanced system-LSI manufacturing at 0.18 micron or finer. The company said the annex was scheduled to start operating in April 2001 and set a target for about 40% of its system-LSI output to use 0.18-micron-or-beyond processes in 2002. Those were company plans and a target, not verified results. Toshiba’s Oita facility announcement.
- Toshiba and Sony’s Emotion Engine venture: A March 1999 announcement described an Oita production venture for the Emotion Engine using 0.18–0.15-micron process technology. This is evidence of separate system-chip activity, not of Toshiba’s DRAM retooling. Toshiba and Sony’s announcement.
- NEC semiconductor research: NEC’s 1998 annual-report material said the first phase of its UC Plant research line began operating in April 1998 and described research into sub-0.18-micron processes using electron-beam exposure and argon-fluoride excimer-laser lithography. This establishes related R&D activity, not a separate confirmation of the reported DRAM production change. NEC’s 1998 annual-report material.
How the report fits the period’s process transition
As broader industry context, TSMC’s 1997 annual-report material projected that its 0.18-micron CMOS logic process would enter volume production in early 1999. That forecast concerns foundry logic, not NEC and Toshiba’s DRAM programs; logic and memory process plans should not be treated as interchangeable. TSMC’s 1997 report.
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How firmly is the NEC–Toshiba DRAM change established?
The specific claim that both companies were retooling DRAM fabs for 0.18-micron line widths is directly supported here by EDN’s August 2000 trade report. The available Toshiba releases substantiate separate system-LSI plans, and NEC’s annual-report material substantiates separate process research; neither is a corporate confirmation of the particular DRAM transition. The careful historical conclusion is therefore that EDN reported the transition and the companies’ distinct strategies—not that NEC and Toshiba jointly announced it.
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