Ainekko announced its merger with Veevx on January 29, 2026, combining Ainekko’s open silicon direction with Veevx’s embedded-AI experience and MRAM-based iRAM memory. The announcement set out a platform strategy, not proof that a finished chip had taped out or that all of the memory technology is open source. In June, Ainekko said its CORE-ET platform had been accepted as an OpenHW Foundation project; that update still does not establish that iRAM’s analog-level IP is publicly available or openly licensed.
What Ainekko and Veevx announced
Ainekko said the companies would merge under the Ainekko name. The company described the combination as adding Veevx’s iRAM memory technology, embedded-AI experience, and team to Ainekko’s open silicon platform. The announcement followed Ainekko’s acquisition of Esperanto Technologies intellectual property, including a many-core RISC-V architecture and toolchain. Ainekko’s merger announcement presents these points as the company’s strategy and description of its technology.
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Ainekko’s current site organizes the platform around three elements: RISC-V many-core compute, MRAM-based iRAM memory, and an open software stack. It describes the intended use as edge-AI inference and the design approach as composable silicon. These are Ainekko’s descriptions, not independent confirmation of product performance or availability. Ainekko’s company site
What is iRAM MRAM, and what does it add?
In Ainekko’s terminology, iRAM is its MRAM-based memory technology. The company positioned it as high-density, non-volatile memory with SRAM-like performance, intended for edge AI and embedded inference. The merger announcement does not provide independently measured speed, energy use, density, or cost figures, so those descriptions should be read as product claims rather than benchmark results.
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The strategic fit is that Veevx brought memory and embedded-AI expertise to Ainekko’s RISC-V compute and software effort. That combination could let the company develop compute and memory as parts of one platform; the announcement does not establish that a commercial system is already available or that this integration has been validated in a finished product.
What the first chip design was supposed to show
EE Times reported on January 30, 2026, that Ainekko planned its first tape-out for the beginning of Q2 2026 using a TSMC 16-nm shuttle wafer. The proposed design paired eight Esperanto Minion small RISC-V cores with Veevx MRAM replacing some SRAM. EE Times described the design as based on an earlier Veevx AI accelerator, with Esperanto RISC-V cores replacing Arm cores. This was a reported plan; the sources reviewed do not confirm that the tape-out took place. EE Times’ January report on the merger and planned design
In that report, Ainekko CTO Roman Shaposhnik gave a preliminary estimate that the MRAM implementation could use about 25% less die area than SRAM. This was a company estimate conveyed in an interview, not an independently verified measurement of a completed chip. The report does not supply a broader apples-to-apples comparison of MRAM, SRAM, and DRAM.
Is Ainekko’s MRAM technology open source?
Not all of it is established as open. In a January 2026 EE Times interview, Ainekko said it intended to open-source RTL, but had not decided how to handle Veevx’s analog-level MRAM technology. The interview also reported that whether Veevx IP would become a commercial product was undecided at that time. CEO Tanya Dadasheva’s statement, “We’re definitely open-sourcing everything at the RTL level,” referred to RTL and should not be read as a commitment that analog-level iRAM IP would also be published under an open license. EE Times’ interview on Ainekko’s open-source plans
In June 2026, Ainekko announced that CORE-ET Silicon Platform had been accepted as an OpenHW Foundation project. The announcement describes many-core 64-bit RISC-V compute, vector/SIMD extensions, a network-on-chip architecture with MRAM-based memory, flexible system interfaces, an architecture emulator, and tools for AI inference frameworks. Ainekko says the architecture, RTL, and tooling are openly available. This is meaningful evidence of an open platform project, but it does not specify that iRAM’s analog-level implementation has been published, is licensed for public use, or can be obtained by developers. Ainekko’s CORE-ET announcement
Ainekko’s site calls its substrate open and identifies AI Foundry and the OpenHW Group of the Eclipse Foundation. Its GitHub repository describes a composable inference-to-hardware stack and displays an Apache-2.0 license. Neither the site description nor a repository license alone establishes the licensing or accessibility of every component mentioned in the merger, particularly analog MRAM IP. Ainekko’s GitHub repository
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the merger means for RISC-V edge AI
The announced direction is to combine RISC-V compute, an open software and hardware platform, and memory technology aimed at embedded inference. If delivered as described, a platform that treats compute, memory, and software as composable building blocks could give developers a different route to designing edge-AI systems. Ainekko CEO Tanya Dadasheva compared the vision to “what Linux did for operating systems and Kubernetes did for cloud infrastructure”; that is the company’s analogy, not evidence that the platform has achieved comparable adoption or ecosystem maturity. Ainekko’s announcement
In the January interview, Dadasheva said, “The chips themselves are not the goal for us,” describing a focus on composable building blocks and libraries and saying the company did not intend to sell chips in volume. That statement records the CEO’s stated business direction at the time; it does not guarantee the company’s current commercial model. EE Times’ January interview coverage
For developers and organizations assessing the platform, the practical questions are whether the relevant RTL and tools are accessible under clear licenses, whether the analog memory IP can be used and on what terms, and whether planned silicon and software support are delivered. The announcements establish the platform’s direction and CORE-ET’s project status, but do not answer all of those implementation and availability questions.
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