Ultra-thin silicon wafers emerged through a sequence of manufacturing changes: first, grinding was used to thin completed device wafers from the backside; then finer grinding was paired with etching or polishing to reduce damage; finally, temporary carriers and reinforced-edge methods made fragile wafers easier to process. The right thickness and process depend on the device and package—not on one universal definition of “ultra-thin.”
Why do semiconductor wafers get thinned?
Removing silicon from the backside of a finished device wafer can reduce the thickness of the final package and enable compact or stacked structures. The IEEE Electronics Packaging Society’s Heterogeneous Integration Roadmap, 2020 version discusses thinning for low-profile single- and multichip packages, stacked memory, wearables and image sensors. The required thickness varies by application and by the device and packaging flow.
Backside thinning is distinct from flattening a substrate wafer. A wafer manufacturer first slices a single-crystal ingot and flattens and finishes the resulting substrate. Device fabrication then builds structures on the front side. If the completed device needs a thinner profile, material is removed from its backside. The historical account in “Grinding of silicon wafers: A review from historical perspectives” (2008) traces grinding’s use in both wafer flattening and thinning completed device wafers; those are different stages with different purposes.
How are silicon wafers made thinner?
The process developed around a practical trade-off: mechanical grinding removes silicon productively, but it can leave subsurface damage and stress that weaken a thin wafer. Later process flows retained grinding for bulk removal and added gentler finishing steps to improve the backside. Equipment, wafer diameter, flatness requirements, slicing methods and polishing choices all affected the evolution; wafer-size growth alone does not explain every change.
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1. Remove most of the silicon by grinding
Backgrinding mechanically removes material from the backside of a device wafer. It is a productive, cost-conscious way to reduce thickness, but the grinding action can create a damaged layer and lower wafer strength. Fine grinding can improve the finish, though grinding alone does not eliminate the damage concerns. The 2020 review “Ultra-thin wafer technology and applications” describes these trade-offs.
2. Relieve grinding damage with etching or polishing
After grinding, wet chemical etching or plasma dry etching can remove damaged silicon; chemical-mechanical polishing (CMP) can be added when a smoother surface is needed. These are complementary steps, not alternatives to all grinding: grinding handles efficient material removal, while etching or polishing improves the resulting surface. Fraunhofer ENAS describes a representative sequence of temporary adhesive bonding, rough and fine grinding, wet etching or plasma etching, optional CMP, and carrier debonding on its temporary wafer bonding and wafer thinning page.
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Fraunhofer ENAS reports rough-grinding rates of 200–300 μm/min and fine-grinding rates of 1–10 μm/min for its described process. It also reports surface roughness below 20 nm after grinding, below 10 nm after etching, and reducible to 1 nm with CMP. These are the institute’s process figures, not guaranteed rates or surface results for every tool, wafer or production line.
How thin can a silicon wafer be?
“Ultra-thin” has no single cutoff across the literature. A 2020 review describes ultra-thin wafers as typically less than 200 μm; a 2015 review focuses on wafer and die challenges below 100 μm; the IEEE roadmap describes the region below about 50 μm as one where gentler removal becomes important. Each threshold belongs to its source’s context, rather than defining a universal boundary.
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The IEEE roadmap reports starting foundry wafers at 0.7–0.8 mm and says conventional abrasive rotary grinding can reach about 50 μm with good total thickness variation (TTV) across a 300 mm wafer. In that roadmap context, thinner dimensions call for gentler removal—such as CMP, wet etching or dry etching—to obtain smoother, lower-stress surfaces. Final die thickness can vary substantially by application. The roadmap’s very thin image-sensor and experimental submicron dielet examples refer to distinct structures and process flows, not a general capability for every wafer.
The 2015 review, “Ultrathin Wafer Pre-Assembly and Assembly Process Technologies”, identifies bow, strength, handling, TTV, dicing and package assembly as challenges below 100 μm. A wafer’s practical lower limit therefore depends not only on how much silicon a tool can remove, but also on whether the wafer can survive subsequent handling and processing.
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How are ultra-thin wafers handled without breaking?
As a wafer becomes thin and flexible, support becomes part of the thinning process. One approach temporarily bonds the device wafer to a carrier. The carrier supports it during grinding and surface treatment; a controlled debond step releases it afterward. The process must limit stress and avoid cracks during both thinning and release. The 2020 review and Fraunhofer ENAS’s process description discuss carrier-supported flows.
Another approach, DISCO’s TAIKO process, grinds the center while leaving a thicker peripheral silicon ring. DISCO reports an approximately 3 mm retained outer edge in its TAIKO process description. The ring supports the thinned center and can reduce handling demands, but uses wafer area that could otherwise be available for devices. The review literature also notes that the ring can complicate packaging if it has to be removed.
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How the approaches compare
| Approach | Thickness and surface | Support and trade-offs |
|---|---|---|
| Conventional mechanical backgrinding | The IEEE roadmap describes reaching about 50 μm with good TTV across a 300 mm wafer. Grinding is productive but leaves subsurface damage and mechanical stress; see the roadmap and the 2020 review. | Support method and breakage risk depend on the flow; a universal comparison is not stated in the cited sources. |
| Grinding followed by etching or CMP | Gentler removal is used below roughly 50 μm in the roadmap context. Fraunhofer ENAS reports process-specific roughness figures, but a universal final-thickness limit is not stated. | Etching removes grinding damage; CMP can further smooth the surface. Throughput and cost comparisons against other flows are not stated as head-to-head values by Fraunhofer ENAS. |
| Temporary carrier bonding | Used to support a wafer during thinning and surface treatment; an achievable final thickness is not stated as a universal value by Fraunhofer ENAS. | Provides mechanical support during processing, then requires debonding without cracking the wafer. The steps described by Fraunhofer ENAS include temporary bonding, grinding, optional etching and CMP, and release. |
| TAIKO retained-edge grinding | The center is thinned while a thicker outer silicon ring remains; DISCO reports an approximately 3 mm retained edge. A universal center thickness is not stated by DISCO. | The ring supports the center but reduces usable area and can complicate packaging if it must be removed, according to the 2020 review and DISCO. |
These approaches are not a single ranking. Choosing between them involves the target thickness, TTV and bow, residual damage and stress, breakage risk, process cost and throughput, usable wafer area, and compatibility with dicing, stacking, backside processing and package assembly. The cited sources do not provide a universal head-to-head winner across those criteria.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What does the 20 μm power-wafer milestone show?
On 29 October 2024, Infineon announced that it had handled and processed 20 μm-thick, 300 mm silicon power wafers in a high-scale fab, and said the process had been qualified and used in Integrated Smart Power Stages delivered to first customers. Infineon called it the world’s thinnest silicon power wafer; that superlative, qualification status and customer-delivery statement are company claims in its announcement, not independently verified comparisons in the sources cited here.
Infineon also said the thinner substrate halves substrate resistance and reduces power loss by more than 15% in power systems compared with conventional silicon wafers. Those are the company’s stated comparisons for its power systems, not performance figures that apply to other devices. The company identified metal-stack thickness, wafer bow, wafer separation and backend assembly as challenges its process addresses. Its 2024 announcement forecast that the technology would replace conventional technology within three to four years; that was a forecast, not a confirmed outcome.
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