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An FPGA-based remote radio head (RRH)—called an O-RU in O-RAN architectures—should be designed from its radio configuration and network boundary inward. Define the bands, channel bandwidth, antenna count, output power, functional split, fronthaul, timing, and deployment conditions first; then allocate signal-processing tasks and select a platform whose converter links, packet interfaces, resources, power envelope, and supported IP fit that design. Legacy CPRI-based RRHs and O-RAN 7.2x O-RUs share some radio-side functions, but their fronthaul architectures are not interchangeable.
Start with the radio and system requirements
An FPGA is not a radio architecture by itself. Its required resources depend on what the radio must transmit and receive, which processing is assigned to the radio unit, and how that unit connects to baseband processing. Write down the system requirements before comparing FPGA families or vendor enablement packages.
- Radio configuration: generation, operating bands, channel bandwidth, number of transmit and receive paths, antenna arrangement, and required RF output power.
- Functional split: which signal-processing functions live in the O-DU or other baseband equipment and which remain in the RRH/O-RU. This determines the data crossing the fronthaul and the processing needed locally.
- Converter and RF chain: ADC/DAC requirements, converter interface standard and lane rate, RF transceiver and up/down-conversion arrangement, power amplifier, filtering, and antenna connection.
- Fronthaul and timing: interface type, port count and line rate, packet handling, timestamps, synchronization method, and the required interoperability profile.
- Deployment envelope: enclosure, available power, cooling, size, ingress protection, and reliability requirements for the installation environment.
These decisions are coupled. For example, antenna count, channel bandwidth, sampling format, compression, and any beamforming assigned to the radio unit affect the datapath and interface load. A platform choice made before settling those responsibilities can leave the design short of I/O, memory, processing capacity, or thermal headroom.
Choose the architecture generation and split
RRH describes radio equipment placed closer to the antenna and connected to baseband processing over a fronthaul. The term spans different generations of systems. The 2011 RRH discussion describes a distributed radio architecture in the context of CPRI; contemporary O-RAN designs describe an O-DU-to-O-RU boundary and packet-based 7.2x transport. Keep the two contexts distinct rather than treating CPRI and O-RAN as names for the same interface. See the historical EE Times RRH article for the CPRI-era context.
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| Design context | What the fronthaul connects | What to establish before implementation |
|---|---|---|
| Legacy CPRI-era RRH | Radio-side equipment and baseband processing over a CPRI-oriented distributed radio link. | Whether the project actually requires CPRI, the applicable interface and timing requirements, and which functions are assigned to the radio-side equipment. Do not assume an O-RAN packet profile applies. |
| O-RAN 7.2x O-RU | O-DU and O-RU, with IQ samples carried in packets using formats defined by the O-RAN fronthaul specification. | The selected specification release, functional profile, configuration, and interoperability requirements. The O-RAN specification portal provides public specifications and describes the organization’s technical approval process; select the applicable release there rather than assuming a version. |
The O-RAN Software Community describes its fronthaul implementation as transporting IQ samples between O-DU and O-RU using packet formats defined by the O-RAN fronthaul specification. That description is useful for understanding the boundary, but a design must still be checked against the release and profile it intends to support. See the O-RAN SC transport-layer documentation.
Map the transmit and receive paths
A conceptual transmit path is baseband IQ input, radio-side signal processing as assigned by the split, digital up-conversion and crest-factor processing, digital predistortion where required, converter interface, RF transceiver and upconversion, power amplification, filtering, and antenna. Receive generally traverses the corresponding chain in reverse: antenna and RF front end, conversion, digital down-conversion and any assigned receive processing, then fronthaul transport.
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This is a design-level map, not a mandatory sequence for every O-RU. The functional split, RF architecture, converter arrangement, and selected implementation determine which blocks are present and where they run. MTI lists digital up/down conversion (DUC/DDC), crest factor reduction (CFR), digital predistortion (DPD), JESD204B/C, CPRI/eCPRI and O-RAN 7.2x among its RRH/RU engineering competencies; this is a supplier capability description, not a requirement that every design integrate all listed functions in one FPGA. See MTI’s RRH/RU design capability page.
Partition the work across FPGA, RF hardware, and fronthaul
Translate the chosen split into explicit ownership for each processing block. The FPGA may handle some combination of DUC/DDC, CFR, DPD, converter-interface logic, packet processing, or other radio functions. The RF transceiver performs radio-frequency conversion, while the power amplifier, filters, and antenna complete the transmit chain. The allocation is design-dependent; listing a function as an FPGA capability does not mean it belongs in every implementation.
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For each block assigned to programmable logic, estimate its throughput and buffering needs using the actual channel configuration and data representation. Then check whether the selected device can sustain the required datapath while also serving interface, timing, and control needs. Account for memory and DSP resources, timing closure, and any reconfiguration requirements; a nominal feature list alone does not establish that a complete design will meet its operating constraints.
Make converter, fronthaul, and timing interfaces fit together
Converter interface
Match the FPGA’s available transceivers and clocking to the required ADC/DAC interface, lane count, and lane rate. JESD204B and JESD204C are examples of converter-link standards used in RRH designs, but the standard name alone is insufficient: confirm the exact converter configuration, supported rates, clocking compatibility, and FPGA resources for the planned channel count.
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Packet fronthaul
For an O-RAN 7.2x design, verify the packet interface and processing against the intended O-RAN release and interoperability profile. Fronthaul line rate is only one part of the fit: the design also needs the required packet handling and any timestamp or synchronization behavior assigned to the O-RU. For a CPRI-era design, validate the CPRI-specific requirements instead of assuming an eCPRI/O-RAN implementation is a drop-in replacement.
Synchronization
Timing is a system requirement, not a late add-on. Determine the synchronization behavior required by the radio and network, and verify that the selected FPGA platform, interface IP, clocks, and system design can support it. MTI lists IEEE 1588 PTP and SyncE among its competencies. AMD’s O-RAN Radio Interface documentation lists eCPRI, IEEE 1914.3, IEEE 1588, and SyncE for the documented core; check the documentation version and supported configuration before specifying those features. See AMD’s O-RAN Radio Interface introduction, documentation version 2.3.
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Compare platforms against the actual design
Use the radio configuration and split as the comparison baseline. Vendor pages can establish what a vendor says a particular package or core supports, but they are not independent performance comparisons. For example, Altera describes its Sail River O-RU enablement package for 4T4R and 8T8R designs on Agilex 5 and Agilex 7, including 25GE O-RAN fronthaul and Split 7.2 Cat A support at 200 MHz. Altera states a JESD204C interface rate of up to 32.44 Gbps for the described package. These are vendor-published capability claims on its wireless solutions page, not independent measurements or proof that every configuration meets a particular project’s needs.
AMD’s documentation describes its O-RAN Radio Interface core in systems based on Versal ACAP, Zynq UltraScale+ MPSoC, and Zynq UltraScale+ RFSoC. Treat the listed platforms and protocols as documentation for the referenced core, not as a like-for-like benchmark against another supplier. Confirm current product status, configuration support, IP availability, licensing, and tool flow when making a project decision.
| Selection axis | Question to resolve |
|---|---|
| Radio and channel configuration | Does the platform have enough suitable converter interfaces, transceivers, DSP and memory resources for the assigned antenna paths, bandwidth, sampling format, and radio processing? |
| Fronthaul and timing | Does the proposed interface and IP support the required port rate, packet handling, timestamping, synchronization, and selected standards profile? |
| Implementation risk | Are the necessary IP, development tools, configuration support, vendor support, lifecycle, and licensing acceptable for the project? |
| Physical deployment | Can the full design meet the power, cooling, size, enclosure, ingress-protection, and reliability constraints? |
The cited material does not establish an independent apples-to-apples comparison of platform performance, power, cost, or bill of materials. Do not infer a vendor ranking from product-page capability figures.
Turn the architecture into an implementation plan
- Freeze the system boundary: document the radio configuration, functional split, fronthaul type and profile, timing requirements, and operating environment.
- Draw the end-to-end data paths: show transmit and receive processing from fronthaul to antenna and back, marking which device owns each block.
- Specify each interface: record converter standard and lane requirements, fronthaul ports and protocol needs, clocks, and synchronization behavior.
- Build a platform fit matrix: compare candidate devices and supported IP against the same requirements, including resource needs, tools, lifecycle, licensing, and thermal constraints. Keep vendor-stated capability separate from independently measured project results.
- Validate system behavior: verify converter links, packet transport, timing, and the complete datapath together under the intended configuration. Passing one interface check does not establish that the full radio system meets its requirements.
For an O-RAN design, resolve the exact specification release and interoperability profile before treating protocol support as complete. For either architecture generation, a usable FPGA solution is the one that closes the radio, data-interface, timing, and deployment requirements as a system—not simply the one with the most listed features.
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