Chiplets can let semiconductor teams reuse silicon across product variants, combine functions built on different process technologies, and split very large designs into smaller dies. But reuse does not make a system plug-and-play: interfaces, packaging, test, qualification, supply-chain agreements and system integration still determine whether a chiplet design delivers its intended value.
What is a chiplet?
A chiplet is a modular silicon die integrated with other dies in one package to form a larger system. It may provide a specialized function, such as compute, acceleration, I/O or memory, or serve as a reusable design block. Unlike a conventional monolithic system-on-chip (SoC), a chiplet system distributes functions across multiple dies connected inside the package.
The idea has a long history. In a 1965 article, Gordon E. Moore wrote, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” AMD reproduced the passage in its December 2024 whitepaper on the chiplet ecosystem. Modern chiplet integration puts that proposition into practice, while adding demanding requirements for high-speed package links, testing and system-level coordination.
What does chiplet reuse mean?
Reuse can mean carrying a functional die into several products, combining reusable IP or functions made on different process nodes, or integrating dies from multiple suppliers. Instead of redesigning one large die for every product, a company may keep a common component and change other parts of the package to create a product family.
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DARPA’s CHIPS program described a vision of discrete, modular, reusable IP blocks assembled using existing and emerging integration technologies. Its program description also stresses that broadly adopted electrical and physical interface standards are necessary to support that vision. Reusable silicon can reduce repeated design work, but the benefit depends on stable interfaces, reusable design collateral and enough products to spread the integration effort across.
Why split a system into chiplets?
Two common design motives are partitioning a large design into smaller dies and matching different functions to different process technologies. These approaches can overlap, but they solve different problems.
| Approach | What it does | Potential value | What still has to be solved |
|---|---|---|---|
| Homogeneous partitioning | Divides a large design into smaller dies made on the same process. | Smaller dies may reduce the yield penalty associated with very large dies. | Actual economics depend on the process, partition, known-good-die screening and assembly yield. |
| Heterogeneous integration | Combines functions or IP made using different process technologies. | Each function can use a process suited to its needs, potentially improving the system’s power, performance, area or cost balance. | Different dies must work together through their interfaces, package and system architecture; integration adds complexity. |
Neither approach guarantees lower cost or better performance. The Open Compute Project’s 2024 ODSA whitepaper treats chiplet adoption as a case-specific decision connected to wider product strategy, not a universal replacement for monolithic SoCs. It identifies potential economic and scaling benefits for large leading-edge designs, while emphasizing that architecture, packaging, testing and manufacturing choices affect the result.
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How standards make reuse more practical
UCIe: a die-to-die interface standard
The UCIe Consortium describes Universal Chiplet Interconnect Express (UCIe) as an open industry standard covering package-level die-to-die I/O physical layers, protocols and a software stack. It leverages PCIe and CXL standards, and its stated aim is to make it easier to mix and match chiplet components from multiple vendors. A common standard can reduce the need for every pair of suppliers to invent a new connection, but it does not by itself make components interoperable in every system.
As listed on the consortium’s official specifications page accessed October 4, 2026, UCIe 3.0 includes published data rates of 48 GT/s and 64 GT/s, an extended sideband channel up to 100 mm, new signaling and management features, and backward compatibility with earlier versions. These are specification features, not independent measurements of application-level performance. Link data rates alone do not determine system throughput: protocol overhead, topology, package implementation, power and workload all matter.
The consortium says UCIe 2.0 added optional system manageability and design-for-test/debug architecture, as well as support for 3D packaging. Those capabilities can help address system integration and test needs, but they do not remove the need to validate a particular combination of dies and package.
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OCP Foundation Chiplet System Architecture
The Open Compute Project’s Foundation Chiplet System Architecture (FCSA) is ecosystem work aimed at architecture- and vendor-neutral definitions of chiplet types, interfaces and integration methods. It is related to Arm’s Chiplet System Architecture, while FCSA is intended to be CPU-architecture-neutral. Its categories include compute, accelerator, I/O, memory and system-expansion chiplets.
FCSA describes integration in layers, from system design and functional interfaces through transport and physical integration. Among the transport options it names are UCIe, AMBA CHI-C2C, CXL and PCIe. This kind of framework can help teams describe and organize an integration, but it is not evidence of a mature plug-and-play marketplace or a guarantee that independently designed parts will work together.
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What chiplet reuse does—and does not—save
The strongest case for reuse is usually strategic as well as technical: preserve a function that works, then differentiate products around it. The business value still depends on the cost of designing, validating and supporting the complete package.
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- Design effort: Carrying a functional die across product variants can avoid repeating some design work. The reusable interface, software and integration collateral must remain suitable for each product.
- Product differentiation: Teams can combine a common die with different compute, I/O, memory or accelerator choices. This can be useful when a monolithic design would be difficult or uneconomic to tailor, but each configuration still needs integration and validation.
- Yield economics: Smaller dies can reduce exposure to defects across a very large die, but known-good-die screening and package assembly introduce their own yield considerations. The net outcome depends on the process and implementation.
- Process choice: A system can use different process technologies for different functions. That flexibility may help balance power, performance, area and cost, but creates more interfaces and manufacturing interactions to manage.
- Interconnect and package: Bandwidth, power, cost, substrate or interposer choice, and 2D, 2.5D or 3D integration are coupled decisions. A faster interface is not automatically a faster or more efficient product.
The market and cost figures often cited around chiplets need context. The OCP ODSA whitepaper (2024) reports a Yole projection of a $48 billion market in 2024 growing to $204 billion by 2032; this is the whitepaper’s attribution to Yole, not a separately verified original Yole report. The same whitepaper says the target for semiconductor die test cost should not exceed 20% of product die cost. That is a stated target in the paper, not an observed industry average.
In a 2023 OCP article, Bapi Vinnakota wrote that 60% or less of the logic in domain-specific accelerators is actually domain-specific. This is the author’s observation about domain-specific accelerators, not a universal statistic for all accelerators. It illustrates why reuse can be attractive, but it does not establish that a chiplet design will save a particular team money.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why a reusable die still needs substantial system engineering
A chiplet is one part of a packaged product, not a standalone solution to architecture or manufacturing risk. Bapi Vinnakota, an engineer at Lawrence Berkeley Laboratory, described the challenge in OCP’s 2023 “Building An Open Chiplet Economy”: “The intricacies of designing and manufacturing chiplet-based products are multifaceted and complex, driven by the simple fact that a chiplet-based product consists of multiple silicon die(chiplets), integrated into one package.”
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Quick Recap
- Compatibility: Teams must align functional behavior, protocols, physical interfaces, electrical characteristics and system assumptions. A shared interface standard is only one layer of compatibility.
- Package design: The substrate, interposer or 3D stack must support the required connections, bandwidth, power delivery and thermal behavior. These choices affect cost and performance.
- Test and debug: Die probe, known-good-die policy, package-level test and debug access need to be planned. A die that passed its own tests may still fail to operate correctly in the assembled system.
- Qualification and reliability: The complete configuration needs validation for its intended use, including interactions among dies and package. OCP identifies device qualification, security, interoperability, supply chain and packaging as barriers to broader adoption.
- Ownership and supply: Multi-vendor products need clear agreements about known-good dies, where inventory is held and for how long, and which party is responsible for product quality.
How to decide whether a chiplet strategy fits
- Start with the product strategy. Identify the functions that genuinely need to vary across products and which could remain common. Chiplets are most compelling when reuse or process specialization has enough value to justify package-level integration.
- Choose the partition for a reason. Decide whether the main goal is to divide a large same-process design, combine functions from different nodes, reuse a die across variants, or integrate suppliers’ components. A partition should solve a product problem, not merely increase the die count.
- Specify interfaces and system assumptions. Select suitable functional, transport and physical interfaces, then document bandwidth, power, protocol, management and test requirements. Standards help define boundaries; system compatibility still has to be demonstrated.
- Evaluate package and manufacturing together. Compare package options alongside interface needs, die sizes, screening strategy and assembly yield. A die-level cost or yield estimate alone cannot establish total product economics.
- Plan qualification and accountability. Decide how each die and the assembled package will be tested, who owns failure analysis and product quality, and how multi-vendor inventory and known-good-die commitments will work.
- Compare against a monolithic alternative. Assess the complete design, manufacturing and product-lifecycle trade-offs for the actual workload and product mix. The outcome is implementation-specific; chiplets are an option for particular scaling and reuse problems, not a default architecture.
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