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An image-processing system turns light into electrical signals, arranges those signals as pixels, moves the resulting video through interfaces, and applies processing—often in an FPGA. Each stage shapes what the next stage can do: the sensor and shutter affect image capture, the pixel format affects color and bandwidth, and the pipeline architecture trades latency against buffering flexibility.
This guide follows the sensor concepts and FPGA example in Adam Taylor’s Hackster.io project, “Lights, Lens, and Logic,” published January 6, 2025. Its hardware and timing details below describe the project’s choices, not independently verified specifications or performance measurements.
How does an image sensor turn light into pixels?
An image sensor contains an array of photosensitive pixels. Photons reaching the array produce electrical signals; the system reads those signals and represents them as digital image data. The pixel array is only the starting point: sensor structure, readout method, color filters, and output interface all influence the data that an image-processing pipeline receives.
CCD and CMOS sensors
In the project’s overview, a charge-coupled device (CCD) accumulates charge in pixel “potential wells.” The charge is shifted through the device for readout and is generally digitized by an external analog-to-digital converter (ADC). A complementary metal-oxide-semiconductor (CMOS) sensor instead uses photodiodes with conversion and digital integration on the sensor chip.
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Taylor describes CMOS sensors as common because their operation and digital integration are easier, while noting that CCDs remain in some high-end imaging applications. That is a high-level comparison, not a universal ranking of image quality, noise, speed, or cost. Actual performance depends on a sensor’s design and the imaging task.
Quantum efficiency and sensor illumination
Quantum efficiency (QE) is the ratio of incident photons to detected photons. It is one way to describe how effectively a sensor converts incoming light into a measurable signal. The project also distinguishes front-illuminated and back-illuminated sensor structures; it does not establish a numerical QE comparison between them.
Which sensor type and shutter suit the imaging task?
Choose based on what the camera must see and how the subject moves. The project discusses visible and near-infrared imaging as well as imaging beyond the visible spectrum; the suitable sensor depends on the target wavelengths and the system design. It also contrasts line-scan and two-dimensional sensors, which capture images differently.
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Line-scan or area imaging
A line-scan sensor captures a line of pixels at a time. Relative motion between the sensor and target supplies the movement needed to build a two-dimensional image. This can suit imaging a moving surface or object along a production line, but it relies on that motion and on coordinating image acquisition with it.
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A two-dimensional (2D) sensor captures an area of the scene rather than relying on target motion to assemble the image. It is the more direct fit when the system needs a full-frame view of a stationary or independently moving scene.
Rolling or global shutter
A rolling shutter reads the image line by line, so different rows represent different moments. If the subject or camera moves during readout, straight objects can appear skewed or otherwise distorted. A global shutter captures the array in synchronization, making it a more suitable choice when the scene contains fast motion. The trade-off is a design choice: match shutter behavior to the motion and timing requirements rather than assuming one is best for every camera.
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| Choice | How capture works | Practical implication |
|---|---|---|
| Line-scan sensor | Captures one line at a time; target or sensor motion builds the 2D image. | Useful when acquisition can be coordinated with motion; does not provide a full area image in a single capture. |
| 2D sensor | Captures an area of the scene. | Does not require target motion to assemble a 2D image. |
| Rolling shutter | Reads the image line by line. | Motion during readout can distort the image. |
| Global shutter | Captures the array in synchronization. | Can avoid the line-timing distortion associated with rolling readout for moving subjects. |
How does a sensor capture color, and what does that cost?
A monochrome sensor measures brightness without separating it into red, green, and blue channels using a color-filter mosaic. A common color approach places a Bayer filter over the sensor: a repeating 2 × 2 pattern contains one red filter, one blue filter, and two green filters. Each pixel therefore samples one color component, not a complete RGB value.
Debayering estimates the missing color components from neighboring samples to reconstruct RGB pixels. Because those colors are interpolated rather than directly measured at every pixel, reconstruction can lose some spatial detail. The method is useful for producing color images from a sensor array, but the output should not be mistaken for three independently captured color values at every photosite.
RGB and YUV 4:2:2 representation
Pixel representation also affects bandwidth. In the project’s example, RGB at 8 bits per channel uses 24 bits per pixel. Its YUV 4:2:2 example uses 16 bits per pixel by sharing chroma information between two pixels. These figures describe those stated representations; color formats and packing schemes vary, so a design must confirm the exact format at each interface.
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| Representation in the project | Stated data per pixel | What it means |
|---|---|---|
| RGB, 8 bits per channel | 24 bits per pixel | Three 8-bit color channels are represented for each pixel. |
| YUV 4:2:2 style | 16 bits per pixel | Chroma is shared between two pixels in the described representation. |
How does camera video reach an FPGA?
A video connection has to carry image data and enough timing or synchronization information for downstream logic to interpret it. The project surveys HDMI, SDI, Camera Link, parallel and serial sensor signaling, and MIPI. These are not interchangeable choices: the right interface depends on the camera or sensor output and on the receiving system.
Once video is inside programmable logic, an AXI Stream-style pipeline transfers data between processing blocks. In the project’s explanation, TData carries the payload, TValid indicates that data is available, and TReady indicates that the receiver can accept it. The handshake lets connected blocks coordinate transfers. Frame-start and line-end markers preserve image structure alongside the pixel data. Sending multiple pixels per clock cycle can raise throughput, provided the connected blocks and clocking support it.
Why choose a direct stream or a frame buffer?
The project contrasts a direct streaming path with a memory-backed path. A direct path minimizes buffering and is intended to reduce latency: data moves through processing blocks toward the output without first storing a complete frame. Its timing is less flexible because input and output flow remain closely tied.
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A frame-buffered design stores frames in memory. That can provide more flexibility to manage timing and synchronization and lets a processor access stored frames, but buffering adds delay and requires memory bandwidth and control. The right choice depends on whether minimum latency or access to buffered frames and timing flexibility matters more.
| Architecture | Advantage | Trade-off |
|---|---|---|
| Direct stream with no frame buffer | Minimizes buffering to reduce latency. | Offers less timing flexibility than a memory-backed path. |
| Memory-backed frame buffer | Can support synchronization changes and processor access to stored frames. | Adds buffering and its associated delay. |
What does the Genesys 2 FPGA example contain?
Taylor’s worked design uses a Digilent Genesys 2 development board with a Kintex-7 FPGA and an HDMI video path. The project describes a 720p output target and a 150 MHz AXI Stream clock. Those are settings and implementation choices in the article; they should not be read as guarantees that every design using the board will achieve the same output or timing.
The article describes the board configuration as having 1 GB of DDR3. It names AMD Vivado and Vitis tools and a MicroBlaze V subsystem for control software. It also lists a Digilent DVI2RGB core, Video In to AXI Stream, AXI Stream to Video Out, a Video Timing Controller, an AXI Stream FIFO, register slices, and DDR3 memory support. The direct HDMI input-to-output architecture is the example’s low-buffering path; the memory support and processor subsystem provide components relevant to control or buffered designs.
- Board used: Digilent Genesys 2 with a Kintex-7 FPGA.
- Video path: HDMI input-to-output, with the named video conversion and timing blocks.
- Project targets: 720p output and a 150 MHz AXI Stream clock.
- Control and memory elements named: MicroBlaze V, DDR3 support, FIFO, and register slices.
The Genesys 2 is the physical board used in this example, not a substitute recommendation. Check current availability, board documentation, and compatibility with the intended design before purchasing or building around it.
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Start with the image and timing requirements, then make the interface and architecture choices that follow from them. A practical decision sequence is:
- Define the imaging task. Identify the wavelength range, scene area, and whether the target moves in a way that supports line-scan capture.
- Choose sensor and shutter behavior. Consider rolling-shutter distortion under motion and whether synchronized global capture is required.
- Set the color and pixel representation. Decide whether the system needs monochrome or reconstructed color, and verify how the chosen RGB or YUV format is packed at each stage.
- Match the interface. Select the camera-to-FPGA connection for the sensor or camera output and the system’s data-transfer needs.
- Specify the stream contract. Ensure the pipeline handles data and ready/valid handshaking as well as frame and line markers; account for multiple pixels per cycle if used.
- Choose buffering deliberately. Use a direct stream when reducing latency is the priority, or evaluate a frame buffer when timing flexibility and processor access to stored frames are needed.
Adam Taylor introduces the project with: “Throughout my 24+ years as an FPGA engineer, one application I have often developed is image processing.” The 24+ years figure is his self-reported experience, not an independently measured statistic.
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