A continuous-time (CT) sigma-delta ADC differs from a sampled-input converter in where sampling happens: its analog loop filter operates continuously, and sampling occurs after that filter, just before quantization. The loop shapes quantization noise away from the signal band; a digital low-pass and decimation filter then removes much of that noise and delivers data at a lower rate.
How a sigma-delta ADC converts an analog signal
A sigma-delta ADC uses a feedback loop rather than taking one isolated measurement of the input and directly encoding it at the output rate. The loop repeatedly compares the input with a feedback signal, integrates the difference, and quantizes the result. In a simple one-bit illustration, the modulator emits a rapid stream of ones and zeros whose average density tracks the input.
- Compare: The input is combined with the inverted output of a feedback digital-to-analog converter (DAC). Their difference is the loop error.
- Filter: A loop filter integrates or otherwise shapes that error over time.
- Quantize: A quantizer converts the filtered signal into a coarse digital output.
- Feed back: The quantizer output drives the DAC, closing the loop. The loop filter and quantizer together shape how the input signal and quantization noise appear at the modulator output.
- Filter and decimate digitally: Digital processing keeps the desired signal band, rejects much of the out-of-band noise, and reduces the high-rate modulator stream to a lower-rate output.
Oversampling means the modulator operates faster than the final data rate needed for the signal. Feedback noise shaping pushes more quantization noise out of the band of interest, where digital filtering can attenuate it. Higher-order loops can shape noise more aggressively, but are more difficult to stabilize. For an overview of the basic topology and noise shaping, see Analog Devices’ explanation of sigma-delta ADC principles and the Analog Devices University Program chapter on analog-to-digital conversion.
What makes the continuous-time version different?
In a CT modulator, the loop filter is an analog continuous-time circuit, often implemented with RC components or with transconductance-and-capacitor (C/gm) stages. The signal is sampled at the output of the forward loop filter, before the quantizer. In a discrete-time sigma-delta modulator, sampling occurs at the input instead. That sampling location is the core architectural distinction.
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Because the CT loop filter acts before sampling, it can attenuate some out-of-band energy before that energy reaches the sampling operation. A discrete-time loop samples earlier, so it does not provide that same pre-sampling attenuation at its input. This difference affects anti-alias filtering and the analog implementation, but does not make a CT converter immune to aliasing or eliminate the need to check the full signal path. Texas Instruments (formerly National Semiconductor) describes this architecture and its tradeoffs in its Continuous-Time Sigma-Delta ADCs application note.
What the decimation filter does—and why it adds latency
The modulator’s high-rate output is not usually the finished conversion result. A digital decimation filter performs two linked tasks: it low-pass filters out-of-band shaped quantization noise and resamples the data to a lower output rate. One possible multistage arrangement uses a sinc filter followed by another low-pass stage; the actual filter depends on the device and application.
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Filter design involves tradeoffs among stopband rejection, passband droop, output rate, and latency. A filter that rejects unwanted energy must accumulate and process samples, so the reported conversion result can lag the input. TI’s application note characterizes delta-sigma decimation filtering as generally producing longer latency than pipeline ADCs. The exact delay is device- and filter-dependent; use the target ADC’s data sheet when settling time or timing alignment matters. For a broader view of system-level blocks and design concerns, see TI’s Designing with delta-sigma ADCs educational series.
Where CT sigma-delta ADCs can help
Pre-sampling attenuation and anti-alias filtering
The continuous-time loop filter can attenuate some out-of-band signals before sampling, which may relax the external analog anti-alias filter compared with an architecture that samples at its input. “Relax” does not mean “remove”: required filtering depends on the signal band, out-of-band blockers, mixing products, and the rest of the system. The intended signal must be in the converter’s first Nyquist zone. An intermediate-frequency signal that a Nyquist-rate ADC could directly sample may need to be mixed down before using a CT sigma-delta converter.
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Potential integrator power savings
TI’s circa-2012 application note identifies lower-power integrator-amplifier operation and inherent anti-alias filtering as potential CT benefits, particularly in the high-resolution applications below 100 MSPS discussed in that document. That historical context is not a universal current throughput boundary, nor does it establish that every CT implementation uses less power than every alternative.
Design constraints to account for
- Loop-filter time constants and tuning: The analog RC or C/gm time constants set the loop dynamics. Component and process variation can shift those dynamics, so the cited TI note says they must be tunable. Unlike a switched-capacitor implementation, the loop dynamics do not scale with sampling frequency in the same way.
- Stability: More aggressive noise shaping may require higher-order loop behavior, but higher-order loops are harder to stabilize. Stability and tuning limits are properties to verify for the particular converter, not assumptions to infer from the architecture alone.
- Signal placement and blockers: Check the intended signal’s Nyquist-zone location, input bandwidth, and out-of-band energy. The CT filter provides some pre-sampling attenuation, not blanket protection from aliasing, mixing, or interference.
- Rate and timing: Distinguish the modulator’s internal operating rate from the filtered output data rate. Include decimation-filter latency in control loops, synchronized measurements, and settling-time budgets.
- System implementation: Front-end amplifier, reference, clock, power supplies, board layout, input bandwidth, and filter configuration all affect system performance. Nominal converter resolution alone does not describe end-to-end accuracy or noise.
How to decide whether a CT sigma-delta ADC fits
Compare architectures against the requirements of the complete signal chain, not just a headline resolution. These are useful axes for evaluating CT sigma-delta, discrete-time sigma-delta, and pipeline or other Nyquist-rate converters:
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- Signal bandwidth and position relative to Nyquist zones.
- Required in-band noise or resolution over that bandwidth.
- Modulator clock range and usable output data rate.
- Out-of-band blockers and the resulting anti-alias filtering burden.
- Power and analog front-end requirements.
- Conversion and filter latency, including settling behavior.
- Integration of the amplifier, reference, clocking, and digital filter functions.
- Loop-filter stability, tuning, and sensitivity to process variation.
There is no universal winner across these dimensions. The appropriate tradeoffs depend on the application and the specific device. For quantitative design choices, consult the target converter’s data sheet and application material; general architectural comparisons cannot substitute for model-specific limits.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A product example is not automatically a CT example
TI’s ADS1626 product page identifies the part as an 18-bit delta-sigma ADC with a maximum 1.25 MSPS data rate, differential input, parallel interface, and 93 dB SNR. Those are specifications for that named product, not general properties of sigma-delta ADCs. The product page does not establish that the ADS1626 uses a continuous-time architecture, so it should not be treated as a CT example. See the TI ADS1626 product page for its stated specifications.
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