CHERIoT-Ibex is an open-source 32-bit RISC-V microcontroller core that adds hardware-enforced capability checks to lowRISC’s Ibex design. It is intended to help embedded systems prevent classes of memory-safety errors. You can prototype it on supported FPGA platforms, including Microsoft CHERIoT-SAFE and lowRISC Sonata; SCI Semiconductors has also released an SoC device using it as its MCU core.
What is CHERIoT-Ibex?
CHERIoT-Ibex is an RTL implementation of the CHERIoT capability instruction-set architecture built on the Ibex core. The Microsoft project repository describes it as a 32-bit RISC-V microcontroller implementing CHERIoT alongside RV32IMCB. “RTL” means the hardware design description used to simulate, synthesize, and implement the processor.
Microsoft’s open-source release in February 2023 covered more than the processor hardware: the stack included an executable formal ISA specification, an Ibex-based reference implementation, an LLVM toolchain port, and a privilege-separated embedded operating system. That combination gives developers hardware, software, and specification components to work with rather than only an instruction-set proposal.
How does CHERIoT-Ibex enforce memory safety?
Instead of relying only on software to check pointers, CHERIoT adds capabilities: hardware-tracked values that carry authority and bounds for accessing memory. CHERIoT-Ibex checks capability rules during ordinary data loads and stores, capability loads and stores, instruction fetches through the program-counter capability (PCC), and jump-target calculations for cjal and cjalr. A violation raises an exception, allowing the system to handle or contain the fault rather than silently completing an unauthorized access.
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
The design also documents optional temporal-safety mechanisms. Spatial bounds help prevent access outside an allowed region; temporal safety addresses stale references to memory that has been freed or revoked.
- CLC load filter: When shadow bits indicate that a referenced heap area has been revoked, this feature can clear the tag on a capability as it is loaded. A cleared tag means the loaded value no longer carries valid capability authority.
- TBRE: A background revocation engine documented by the design.
- STKZ: A stack-zeroization engine documented by the design.
These features are configurable; the project does not imply that every deployment must enable every temporal-safety mechanism. The design documentation describes the mechanisms, but the specific configuration and its costs depend on the implementation.
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- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
How does it compare with conventional Ibex?
| Aspect | Conventional Ibex baseline | CHERIoT-Ibex |
|---|---|---|
| Memory-safety approach | Baseline Ibex does not add the CHERIoT capability checks described for CHERIoT-Ibex. | Hardware checks capability rules for data access, capability access, instruction fetches, and selected jumps. |
| Temporal safety | CHERIoT temporal-safety mechanisms are not part of the baseline comparison described by the project. | Optional configurable mechanisms include the CLC load filter, TBRE, and STKZ. |
| Compatibility | Runs its supported RISC-V software. | In backward-compatibility mode, CHERIoT features are disabled and the core is logically equivalent to Ibex for unmodified RV32IMC binaries. |
| Implementation trade-off | Prioritizes a smaller baseline core. | Microsoft characterizes it as a moderate area increase over Ibex, with dynamic and leakage power similar to the original Ibex; the repository reports approximately 60,000 gate equivalents for CHERIoT-Ibex. |
The main design trade-off is therefore stronger hardware-enforced memory protection versus implementation cost and configuration complexity. Microsoft’s repository reports synthesis results for a three-stage configuration: 250 MHz using TSMC 28 nm libraries and 550 MHz using TSMC 5 nm libraries, under the stated slow-slow conditions. These are project-reported synthesis results, not independent benchmarks or guaranteed operating frequencies for a particular chip or FPGA.
Can you run CHERIoT-Ibex on an FPGA?
Yes. The official project README names two open-source FPGA platforms designed for CHERIoT-Ibex emulation and prototyping:
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- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
- Microsoft CHERIoT-SAFE
- lowRISC Sonata
These give developers a way to evaluate and prototype the core on FPGA hardware. The project’s README also reports simulation, formal-verification, and FPGA-validation work. Those activities demonstrate development and validation paths, but do not by themselves establish that a specific board configuration is production-ready for a particular application.
Is there a CHERIoT-Ibex chip or development board to buy?
The project identifies FPGA platforms for prototyping, but the material available here does not establish current retail availability, pricing, or stock for those boards. Check the respective platform maintainers or sellers for current purchasing information.
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- High Performance RISC-V Processor - Equipped with a 32-bit ESP32-C3 chip, 160MHz clock frequency, FPU floating-point unit and 400KB SRAM, ideal for efficient IoT development.
- Dual-Mode Wireless Communication - The ESP32-C3 supports 2.4GHz Wi-Fi (802.11b/g/n) and Bluetooth 5 (LE) with 400KB internal SRAM, 384KB ROM storage and 4MB onboard flash memory.
- COMPACT DESIGN & MULTIPLE INTERFACES - ESP32-C3 mini development board features 11 PWM GPIOs, 4 ADCs and UART/I2C/SPI interfaces and is compatible with various sensors and wearables.
- Extremely Low Power Consumption - The ESP32-C3 SuperMini is a powerful, low-power and cost-effective IoT mini development board, ideal for low-power IoT applications and wearable wireless applications. The deep sleep mode consumes only 43 µA and is therefore ideal for projects with long-term battery operation.
- Secure Encryption Support - Hardware accelerated AES/RSA/HMAC encryption, supports Secure Boot to ensure data security.
There is also a released device beyond FPGA prototypes: the project README notes that SCI Semiconductors released the ICENI SoC device incorporating CHERIoT-Ibex as its MCU core. That establishes an announced device incorporating the design, but does not establish its current availability or suitability for a given product.
The core RTL itself is open-source hardware, not a ready-made chip or board. A team planning a product still needs to select or build a platform, integrate and configure the design, and validate the complete system for its requirements.
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- Latest Version: Higher core clock speed, double memory, more powerful Arm cores, optional RISC-V cores (compared to the 1 series) (This W version has onboard wireless LAN and Bluetooth)
- Switchable Cores: Allows users to choose between dual industry-standard Arm Cortex-M33 cores and dual open-hardware Hazard3 cores
- Compatibility: Delivers a significant performance boost, while retaining software- and hardware-compatible with the 1 series
- Detailed Tutorial: Provides step-by-step guide with MicroPython, C and Processing (Java) Code (The download link can be found on the product box) (No paper tutorial)
- Example Projects: Each project has schematics, wiring diagrams, complete code and detailed explanations (Need extra items)
What is the project’s production status?
Open source does not automatically mean production-ready. On June 20, 2024, lowRISC announced a collaboration with Microsoft to bring CHERIoT-Ibex to production grade. The project’s documented simulation, formal verification, and FPGA validation provide evidence of engineering work, while that collaboration announcement describes a production-readiness effort—not proof that every implementation or deployment has completed qualification.
For engineering decisions, distinguish the core’s documented security mechanisms from the assurance of a particular finished product. A deployment’s configuration, integration, software, and verification all affect whether it meets its threat model and reliability requirements.
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