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The X Architecture is an integrated-chip design approach that combines conventional horizontal and vertical wiring with diagonal interconnect. It can give a digital ASIC more routing choices and, in some designs, shorter wire paths—but it also changes what the physical-design flow must support. It is not simply a different setting in the router.
What is the X Architecture?
Kalyan Thumaty and Robert Lipsey define X Architecture as “the pervasive use of both Manhattan and diagonal interconnect on a chip” in their 2005 EE Times article. Manhattan routing uses horizontal and vertical tracks; X Architecture adds diagonal directions to those conventional paths.
The approach is a superset of Manhattan routing, not a demand to make every wire diagonal. Lower metal layers can remain orthogonal, preserving compatibility with standard-cell libraries and existing IP, while upper routing layers use diagonal tracks. The 2005 article describes this as increasing the available routing directions from four to eight. More choices can make a route more direct or help it work around a block, potentially reducing wire length and via count. Those are opportunities, not guaranteed outcomes for every design.
The name refers to the diagonal paths crossing the familiar grid; it does not mean that a chip’s entire wiring fabric becomes an X-shaped pattern. Layer direction, pitch, blockages, pin access and routing demand still constrain which paths are usable.
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How does diagonal routing compare with Manhattan routing?
| Aspect | Manhattan routing | X Architecture |
|---|---|---|
| Available directions | Four routing directions, as counted in Thumaty and Lipsey’s 2005 article. | Eight routing directions, as counted in the same 2005 article, by adding diagonal choices. |
| Layer strategy | Uses horizontal and vertical routing. | Can retain orthogonal lower layers and add diagonal routing on upper layers. |
| Potential route geometry | A path between two points may need multiple horizontal and vertical segments. | A diagonal segment may make some connections more direct or provide another way around an obstruction. |
| Likely trade-off | Conventional Manhattan-based infrastructure can be used. | Potential wire-length and via-count savings must be weighed against the need for diagonal-aware design and analysis infrastructure. |
The comparison is about routing options, not a universal performance ranking. A diagonal path is useful only when the design’s layer assignments, pins, obstacles and tool flow let it be used effectively.
Which designs are the best fit?
The 2005 article proposes X Architecture particularly for digital-heavy ASICs and application-specific standard products (ASSPs) that have enough routing layers and logic to benefit from additional routing freedom. It gives these target criteria:
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- More than four signal-routing layers above the library cells.
- A near-square chip aspect ratio.
- At least 50% of the chip area occupied by random logic.
These are the authors’ selection criteria, not a universal foundry rule or a guarantee that a design meeting them will benefit. The source presents possible area, performance, power, yield and cost gains as potential advantages; it does not establish that they are achieved on every process node or product.
What changes in the physical-design flow?
Thumaty and Lipsey caution that implementation is not only a routing problem. Floorplanning, placement, optimization, extraction, power-grid design and finishing steps also need to account for diagonal geometry. The details depend on the implementation system and the technology data it supports.
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Floorplanning and pin assignment
Set preferred diagonal directions and pitches with the available routing resources in mind. The source recommends balancing those resources rather than choosing diagonal directions in isolation. Pin assignment must also be X-aware: pin locations and access need to work with the directions the routing layers provide.
Power-grid design and analysis
Align power-stripe direction with each layer’s preferred routing direction; on diagonal layers, that means diagonal stripes. Because the grid geometry affects electrical analysis, IR-drop and electromigration checks need diagonal-aware extraction and analysis. Cadence is the vendor named in the 2005 account, which discusses VoltageStorm extensions for diagonal power-grid analysis.
Placement
With both diagonal and Manhattan paths available, the authors describe a larger octagonal feasible region for placement than the region available with Manhattan routing alone. Placement tools can use that additional freedom to address congestion or shorten connections. Whether it helps depends on the design and on the implementation flow’s ability to model and exploit the geometry.
Routing and optimization
Treat X routing as an extension of Manhattan routing: orthogonal paths remain available, while diagonal paths add choices. The article describes using eight routing directions and region-specific preferences to find routes around blocks. Optimization also needs to account for the added routing options; a router that can draw diagonal paths is not, by itself, evidence that the rest of the flow handles them correctly.
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Extraction and finishing
Extraction must model interactions between Manhattan and diagonal wires so downstream electrical analysis reflects the geometry. The finishing flow must also handle diagonal cases for metal fill, clock shielding and redundant-via insertion, including transitions between different wire directions.
Sign-off
The 2005 article says existing design-rule checking (DRC), layout-versus-schematic (LVS), static timing analysis (STA), crosstalk, signal-integrity, IR-drop and electromigration sign-off tools can continue to be used, subject to support from the implementation system. That qualification matters: a familiar sign-off tool does not remove the need for compatible diagonal geometry and data throughout the design flow.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What do the published figures establish?
The available numerical claims come from Thumaty and Lipsey’s 2005 methodology article, not from a contemporary comparative benchmark. The authors report eight rather than four routing directions and state that X Architecture offers “41% larger placement area for a given timing constraint.” The article’s stated figure does not, by itself, establish a modern-node area reduction, timing improvement or result for a particular chip; it should be read as a claim made in that source, not a general design guarantee.
The article also identifies LEF/DEF version 5.6 as supporting diagonal constructs. That is a version-specific statement from the 2005 material, not confirmation of present-day format, tool or foundry support. Neither the 2005 EE Times nor the EDN republication establishes current adoption levels or a current foundry qualification list.
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Quick Recap
What should a design team verify before choosing it?
- Confirm that the target process, routing stack and implementation tools support diagonal geometry across the stages the design needs—not just in routing.
- Check that library cells, IP pins, blockages and pin assignment leave useful access to the proposed diagonal layers.
- Plan floorplanning, placement, power distribution and signal routing together, including the chosen directions and pitches.
- Verify extraction, electrical analysis, metal fill, shielding, via insertion and sign-off behavior for Manhattan-to-diagonal transitions.
- Compare results against a Manhattan implementation for the actual design and process. Treat the benefits described in the 2005 article as hypotheses to evaluate, not as promised savings.
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