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Start with the system’s coherency boundary
ACE extends AXI with three channels for sharing data between ACE Manager caches and cache-maintenance hardware. It also supports barriers for ordering outstanding transactions and Distributed Virtual Memory (DVM) signaling for maintaining virtual-memory mappings across ACE Managers. These features work only as part of a coherency-capable system: the address map, participating agents, interconnect and maintenance path must agree.
Define memory attributes and Shareable regions
For each address region, specify whether it is Shareable and whether it is cacheable memory or Device memory. ACE distinguishes non-snooping accesses from coherent accesses. ReadNoSnoop and WriteNoSnoop are used for non-shareable or Device memory; coherent transactions are used for Shareable locations that may be held in other coherent caches. Verify that the attributes presented by each requester match the system’s intended treatment of that region.
Classify every master
| Master type | Coherency role | What to establish in the design |
|---|---|---|
| ACE | Participates in the ACE coherency protocol and can interact with other coherent agents through the interconnect. | Identify its cache and maintenance behavior, the Shareable regions it accesses, and the snoops and responses it must handle. |
| ACE-Lite | Provides a smaller subset for one-way I/O coherency. ACE masters can snoop an ACE-Lite master; other managers cannot snoop its cache. | Document the direction of coherency and how I/O accesses interact with the ACE system. Do not treat ACE-Lite as a full ACE cache manager. |
| Non-coherent AXI | Does not participate in ACE snooping. | Define how its accesses are kept consistent with cached data, including any required software or hardware cache-maintenance path. |
These roles describe protocol participation, not a guarantee that every access is coherent. The system still needs an explicit policy for regions and agents.
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Expose and verify interconnect controls
Interconnect features can affect how coherency is controlled and observed. Arm’s CCI-400, for example, supports up to two ACE masters and three ACE-Lite masters, three independent points of serialization, full barrier support, DVM transport, QoS regulation, performance monitoring and a programmer’s view for coherency and interconnect control. Those figures and features describe CCI-400, not a general ACE limit or a requirement for every interconnect. For the chosen implementation, identify the actual configuration, serialization points, maintenance controls and monitoring available to the testbench.
Check transaction legality at the interface
Build protocol monitors and assertions around channel handshakes, response ordering, burst and attribute consistency, and legal coherent transaction encodings. For a cached Manager’s snoop address channel, Arm IHI 0022H.c permits the following snoop transactions:
- ReadOnce, ReadClean, ReadNotSharedDirty, ReadShared and ReadUnique
- CleanInvalid, MakeInvalid and CleanShared
The same specification prohibits these transactions as snoop transactions:
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- ReadNoSnoop
- CleanUnique and MakeUnique
- WriteNoSnoop, WriteUnique and WriteLineUnique
- WriteBack, WriteClean, WriteEvict and Evict
Use these lists specifically to check snoop-address traffic; they are not a substitute for validating all channel rules or transaction encodings in the selected protocol revision. Make monitors report the offending channel, transaction and address so an illegal transfer can be traced to its requester and attributes.
Verify cache-line state and returned data together
A coherent response is correct only when both its data and its effect on ownership and cache state are correct. For each coherent read, write, clean, invalidate and snoop response, check the required state transition as well as the value returned to the requester. Include shared copies, unique ownership, dirty and clean data, and eviction behavior.
Cover transfers of dirty ownership explicitly. In particular, check the interconnect’s writeback behavior when a requester cannot accept dirty data. A scoreboard should track the expected value and relevant ownership across agents, rather than infer correctness from the state reported by one local cache.
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Use the Point of Coherency as the end-to-end observation boundary
Arm defines the PoC for an address as the point at which all blocks that can access that location are guaranteed to see the same copy. Its Cortex-R Programmer’s Guide gives cores, DSPs and DMA engines as examples of such blocks. Use this architectural boundary for system-level data and ordering checks: a local cache hit alone does not demonstrate that every relevant agent can observe the correct value.
At the PoC, check that stores become visible to the agents entitled to access the location and that the observed value respects the required ordering. Include all relevant readers and writers in the checker’s model, including I/O agents where they participate in the system’s coherency design.
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Barriers and outstanding transactions
ACE barriers provide ordering guarantees across outstanding transactions. Create directed sequences that place barriers between writes, reads, cache-maintenance operations and DVM operations. Vary interconnect latency and response ordering, then check that software-visible completion follows the specified barrier semantics. Arm’s cache guidance also requires memory barriers with cache-maintenance sequences, so verify the sequence as a whole rather than treating a maintenance operation’s completion in isolation.
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DVM and address attributes
If the design uses DVM, exercise message transport and virtual-memory changes across the ACE Managers that depend on them. Cross the relevant cases: Shareable and non-shareable mappings, ACE and ACE-Lite requesters, and cacheable and Device attributes. Include negative tests confirming that a non-shareable or Device access does not trigger snoops unintentionally.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Stress concurrency and recovery paths
Directed tests establish specific rules; concurrent tests expose interactions among agents and channels. Combine multiple outstanding requests, backpressure on every channel, simultaneous snoops, dirty data in several caches and contention at each point of serialization.
- Check forward progress and absence of deadlock under sustained backpressure.
- Check that each request receives the required response exactly once.
- Check that competing accesses and snoops preserve the expected cache state and data.
- Check eventual visibility of a store to every agent that can access the location.
Use the implementation’s configured outstanding-transaction limits and serialization behavior as test parameters; do not assume a universal ACE maximum.
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Make the protocol revision an explicit project decision
Arm’s specifications catalog identifies the original ACE specification as superseded by CHI, while AMBA 5 also lists ACE5 alongside AXI5 and CHI. Before writing assertions or interpreting a transaction, record the exact IHI revision and protocol profile the design implements. Establish whether the project targets legacy ACE, ACE5 or CHI; do not assume that a test plan for one applies unchanged to another.
A useful verification plan therefore ties each check to the chosen profile, agent type, address attributes and observation point. That keeps interface legality, snoop behavior, ordering and system-level visibility connected to the architecture the RTL is actually meant to implement.
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