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Hitachi and STMicroelectronics designed SH-5 as a 64-bit successor to the SuperH family with two instruction modes: SHcompact, which retained compatibility with SH-4 software, and SHmedia, a new 32-bit encoded instruction set aimed at high-performance multimedia and SIMD work. The idea was to give existing software a migration path while letting new applications use the architecture’s expanded capabilities.
What was the SH-5?
Hitachi and STMicroelectronics announced SH-5 on October 5, 1999, as a jointly developed 64-bit RISC architecture extending Hitachi’s SuperH family. They targeted uses including home networking, residential gateways, digital television, set-top boxes, in-car navigation, multimedia and video processing, and high-end portable devices.
SH-5 was presented as an architecture for future products, not simply as a standalone processor launch. Its design also anticipated system-on-chip (SoC) integration, including backward-compatible peripheral buses intended to accommodate intellectual-property blocks from both companies.
How could it use two instruction sets?
SHcompact preserved the older software path
SHcompact retained the 16-bit instruction set compatible with SH-4 software. That gave developers a way to carry forward existing applications instead of requiring every program to be rewritten for the new architecture.
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SHmedia added a new path for demanding work
SHmedia used newly designed 32-bit encoded instructions and was intended for high-performance multimedia and SIMD processing. Its wider data model and SIMD-oriented operations provided a route for new code to take advantage of SH-5’s capabilities.
The two modes were not two instruction streams running at once. They were alternative ways for the core to execute code. EDN described an on-board switching engine that let the processor use the older coding for basic or legacy tasks and the newer code for more complex functions. STMicroelectronics U.S. operations director Greville Commins explained the compatibility aim: “This allows us to completely revamp the design, but [make it] still compatible with all the legacy applications that are using the earlier SH products.”
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- ESP32-S3R8 Processor--- Equipped with ESP32-S3R8 Xtensa 32-bit LX7 dual-core processor, up to 240MHz main frequency. Supports 2.4GHz W-i-F-i (802.11 b/g/n) and Blue--tooth 5 (LE), with onboard antenna. Built in 512KB of SRAM and 384KB ROM, with onboard 8MB PSRAM and an external 16MB Flash memory.
- AMOLED Touch Screen--- Onboard 1.8inch AMOLED display for clear color picture display, 368 x 448 resolution, 16.7M color, 178° wide viewing angle. Compared to those traditional LCD displays, the AMOLED screen features precise light-control capability, representing more delicate colors, more picture details, and more vivid video image.
- Onboard Audio Codec---Supports high-quality audio processing, providing clear and high-quality audio input and output. Supports Offline Speech recognition and AI Speech Interaction---Allows access to online large model platforms to support more AI application scenarios.
- For Various Smart Devices---Suitable For Various Smart Devices Development, Can Realize Human-Computer Interaction Function. Supports installing ba|tte|ry inside the case for independent operation. （Note: this version doesn't include ba|tte|ry ） Dedicated Black Case---with removable back cover for easy embedded into the projects and DIY design.
- Sensor and Chip---Onboard QMI8658 6-axis IMU (3-axis accelerometer and 3-axis gyroscope) for detecting motion gesture, counting steps, etc. Built-in SH8601 display driver and FT3168 capacitive touch chip, using QSPI and I2C communication respectively, effectively saving the IO resources.
What performance and hardware figures did the companies announce?
The figures below are specifications reported by Hitachi and STMicroelectronics in 1999 for a 400 MHz, 1.5 V design. They are vendor-announced results, not independent modern benchmark measurements.
| Specification | Announced figure | Qualification |
|---|---|---|
| Power | 600 mW | Hitachi and STMicroelectronics, 1999; specified for a 400 MHz, 1.5 V design. |
| Dhrystone 1.1 | 714 MIPS | Hitachi and STMicroelectronics, 1999; vendor-reported result. |
| Dhrystone 2.1 | 604 MIPS | Hitachi and STMicroelectronics, 1999; vendor-reported result. |
| Throughput | 9.6 GOPS | Hitachi and STMicroelectronics, 1999; vendor-announced figure. |
| Multiply-accumulate throughput | 1.6 GMACS | Hitachi and STMicroelectronics, 1999; vendor-announced figure. |
| Floating-point performance | 2.8 GFLOPS | Hitachi and STMicroelectronics, 1999; specified with the optional floating-point unit. |
| Process technology | 0.15-micron CMOS | Hitachi and STMicroelectronics, 1999; announced design specification. |
| Read/write channels | Dual 64-bit channels | Hitachi and STMicroelectronics, 1999; announced design specification. |
| Internal bus | 3.2 GB/s SuperHyway bus | Hitachi and STMicroelectronics, 1999; announced design specification. |
Why did SH-5 matter to SuperH developers?
The architecture paired continuity with a substantial redesign. SHcompact offered a compatibility route for SH-4 applications; SHmedia gave developers a distinct instruction set for new multimedia and SIMD-focused software. That meant migration did not have to be all-or-nothing: older code could remain on the compatible path while newly developed performance-sensitive code used SHmedia.
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- 2.4GHz Dual Mode WiFi + Bluetooth Development Board
- Support LWIP protocol, Freertos
- SupportThree Modes: AP, STA, and AP+STA
- Ultra-Low power consumption, Compatible with Arduino IDE
- ESP32 is a safe, reliable, and scalable to a variety of applications
The SoC-oriented features were part of the same strategy. Backward-compatible peripheral buses were intended to make it easier to integrate existing Hitachi and ST intellectual-property blocks into systems built around the architecture.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What happened to the SH-5 effort?
In April 2001, Hitachi and STMicroelectronics announced plans to create SuperH, Inc., an independently managed company that would license SuperH cores and complete final development of the 64-bit SH-5. That announcement places SH-5 within a wider processor-core licensing strategy, rather than describing only a single chip product.
Quick Recap
Best Value
- Capacitive Touch Display: Onboard 1.28inch capacitive touch display with 240×240 resolution and 65K color, featuring QMI8658 6-axis IMU with 3-axis accelerometer and 3-axis gyroscope for detecting motion gestures
- Memory and Storage: Built in 512KB of SRAM and 384KB ROM, with onboard 2MB PSRAM and an external 16MB Flash memory, featuring Type-C connector for easy connectivity and updates
- Dual-Core Processor: Equipped with 32-bit LX7 dual-core processor operating up to 240MHz main frequency, supports 2.4GHz Wi-Fi (802.11 b/g/n) and Bluetooth 5 (LE) with onboard antenna
- Battery and Connectivity: Onboard 3.7V lithium battery recharge and discharge header with 6 GPIO pins via SH1.0 connector for flexible project integration
- Low Power Consumption: Supports flexible clock and module power supply independent setting with various controls to realize low power consumption in different scenarios, integrated with USB serial port full-speed controller and GPIO pins for flexible pin function configuration
Rank #4
- Equipped with Xtensa 32-bit LX7 dual-core processor, up to 240MHz main frequency.Supports 2.4GHz Wi-Fi (802.11 b/g/n) and Bluetooth 5 (BLE), with onboard antenna
- Built in 512KB of SRAM and 384KB ROM, with onboard 2MB PSRAM and an external 16MB Flash memory.Type-C connector, keeps it up to date, easier to use.
- Onboard 1.28inch LCD display, round IPS panel, 240×240 resolution, 65K color.Onboard QMI8658 6-axis IMU (3-axis accelerometer and 3-axis gyroscope) for detecting motion gesture.Onboard 3.7V lithium battery recharge/discharge header and GPIO headers
- Supports flexible clock, module power supply independent setting, and other controls to realize low power consumption in different scenarios
- Integrated with USB serial port full-speed controller, GPIO pins allow flexibly configuring pin functions
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