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Embedded SRAM can give AI processors more speed and energy efficiency by keeping frequently used data close to the compute units—or, in compute-in-memory designs, by doing some calculations where the data is stored. It complements rather than replaces high-capacity memory such as HBM: SRAM is fast and precise, but its large bit cells make it costly in chip area.
Why embedded SRAM matters for AI
AI accelerators repeatedly read model weights and intermediate results while performing calculations. When that data must travel across a chip or between the processor and off-chip memory, the transfers add latency and consume energy. Integrating SRAM alongside logic puts a fast working store near the engines that use it, reducing some of that movement.
Embedded SRAM is not a new kind of memory so much as a way to make memory part of the processor or accelerator die. At advanced process nodes, SRAM can be integrated with logic and made available to compute engines as cache, buffers, local storage, or—in specialized designs—a place to perform computation.
This proximity can improve effective bandwidth and reduce the cost of fetching data, but it does not make the capacity problem disappear. SRAM occupies substantial silicon area, so designers balance how much to include against the die area available for compute and other functions.
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SRAM near compute is not the same as SRAM compute-in-memory
Near-memory SRAM
In a conventional processor, SRAM stores data close to compute units, which still perform calculations in their own logic. This can shorten data paths and reduce repeated trips to more distant memory, but data must still move between the SRAM and the compute unit.
SRAM compute-in-memory
SRAM compute-in-memory (SRAM-CIM) performs operations such as multiply-accumulate (MAC) work in or alongside the array where weights are stored. The aim is to reduce movement further by combining storage and computation. It is a distinct architecture, not a feature that follows automatically from putting SRAM on the same die as an AI processor.
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CIM designs may mix memory technologies and digital compute rather than rely on one element for every task. A 2025 Nature paper by Khwa, Wen, Hsu and colleagues described a mixed-precision processor combining SRAM-CIM, memristor-CIM and small digital units. Its design assigns layers or kernels to the memory and number format suited to their accuracy, storage, efficiency and wake-up requirements.
How SRAM-CIM compares with other AI memory choices
| Factor | Conventional memory hierarchy | SRAM-CIM | Memristor-CIM |
|---|---|---|---|
| Data movement | Data moves between memory and separate compute logic; near-die SRAM can shorten the path, while off-chip transfers remain a cost. | Can reduce movement by calculating where weights are stored. | Can combine compact weight storage and computation in the memory array. |
| Latency and wake-up | Depends on the memory level and system design; no comparable system figure is established here. | The Nature paper reports 373.52 microseconds for wake-up-to-response in its mixed-precision processor; this is a result for that design, not a general SRAM-CIM specification. | The same paper’s processor design considered wake-up latency when assigning work; it does not establish a general memristor-CIM wake-up figure. |
| Density and die area | On-die SRAM is fast but uses significant silicon area; off-chip or stacked memory offers a different capacity and packaging trade-off. | Lower storage density than the paper’s memristor-CIM, because SRAM bit cells are larger. | Compact, nonvolatile weight storage in the paper’s design. |
| Precision and accuracy stability | Conventional digital computation can preserve exact digital values, subject to the selected numeric format. | The paper describes lossless digital computation. | The paper notes potential accuracy loss from process variation. |
| Process and implementation status | SRAM can be embedded with logic at advanced process nodes. Marvell reported a custom 2-nm SRAM design for AI XPUs and cloud data centers. | Demonstrated in the Nature paper’s mixed-precision processor; the paper’s results should not be treated as specifications for commercial products. | Also demonstrated in that paper’s mixed-precision processor; no broader commercial availability is established by the cited evidence. |
The Nature paper reports 40.91 TFLOPS/W on ResNet-20 using CIFAR-100 and 28.63 TFLOPS/W on MobileNet-v2 using ImageNet, with less than 0.45% accuracy degradation in those tests. Those figures are results for the paper’s combined architecture and workloads, not a direct, universal comparison of SRAM-CIM against HBM or a standalone product rating.
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Can SRAM compete with HBM?
They address different parts of the memory problem. SRAM’s strength is speed and proximity to logic; its weakness is lower density and high die-area cost. HBM provides high-capacity, high-bandwidth memory in a separate stacked-memory package, while embedded SRAM can serve as a much smaller, faster local store. An AI processor can use both: HBM for a larger working set and SRAM for data that benefits from immediate access.
There is no like-for-like HBM performance comparison in the reported figures here, so those figures do not show that SRAM replaces HBM. Marvell’s lead memory architect Darren Anand described a complementary packaging trade-off: “We have a lot of synergy with some of the packaging and custom HBM work that we’re doing where we can open up more die area on the XPU for compute.” Anand added, “That can help the overall device performance.” The statements describe Marvell’s design rationale, not a measured result for all XPU designs.
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What Marvell announced about custom embedded SRAM
EE Times reported that Marvell claimed an industry-first 2-nm custom SRAM designed for AI XPUs and cloud data centers. The company’s stated maximums are up to 6 Gb of high-speed memory and operation at up to 3.75 GHz. Marvell also claimed up to 66% lower power than standard on-chip SRAM at equivalent densities. These are company claims, not independent comparative test results, and “up to” figures should not be read as guaranteed performance in every implementation.
Anand told EE Times that, in a typical XPU, at least 30% of silicon area is dedicated to SRAM, with some designs exceeding 50% or 60%. That is an interview statement about typical and some designs, not a universal industry statistic. He also said, “We don’t look at it as just plumbing; we look at it as an opportunity for innovation.”
Commercial compute-in-memory: GSI Technology’s Gemini
Commercial CIM examples are emerging, often as specialized accelerators rather than consumer AI chips. In a 20 October 2025 release, GSI Technology summarized a Cornell-led evaluation of its Gemini-I APU on retrieval-augmented-generation (RAG) workloads using datasets from 10 GB to 200 GB. GSI reported throughput comparable to an NVIDIA A6000, more than 98% lower energy consumption than a GPU, and up to 80% shorter total processing time than CPUs. These are figures reported by GSI in its summary of the Cornell study; they are not universal results for other datasets, systems or workloads.
GSI positions Gemini and newer Gemini-II/Plato products for data-center, edge, robotics, drone, defense and aerospace applications. The release establishes a commercial product line and reported evaluation, but does not by itself establish current availability, purchasing terms or suitability for a particular deployment.
Quick Recap
How to judge an AI memory claim
- Check what is integrated. An on-die SRAM cache, a custom embedded SRAM macro and an SRAM-CIM array are different things.
- Look for the workload and comparison baseline. Performance and energy claims depend on the model, dataset, precision, system configuration and what the result is compared with.
- Separate storage from compute. SRAM’s speed and precision can be valuable, but storage density and die area constrain capacity.
- Distinguish research from product evidence. A paper’s prototype results, a vendor’s product announcement and an accelerator evaluation establish different things; none alone guarantees performance in another system.
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