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NHanced Semiconductors is integrating Avalanche Technology’s Space Grade MRAM as boot memory for rad-hard FPGA systems intended for satellite and defense missions. A follow-on collaboration announced in March 2026 places the memory die in a chiplet-based 2.5D package using NHanced’s hybrid-bonding flows. This is a specialist aerospace and defense design-in—not a consumer memory launch or a named satellite deployment.
What NHanced and Avalanche announced
The partnership addresses a specific need in radiation-hardened FPGA system-in-package designs: dependable memory from which a system can boot. NHanced evaluated multiple options and selected Avalanche’s Space Grade MRAM for that role. In Avalanche’s January 26, 2026 announcement, NHanced President Bob Patti said, “We evaluated multiple solutions and picked Space Grade from Avalanche.”
On March 16, the companies described a further integration approach: treating the MRAM die as a chiplet within NHanced’s 2.5D packaging and hybrid-bonding flows. The announcement presents this as an approach for rad-hard FPGA integration, not evidence that every NHanced FPGA product uses the memory or that a particular satellite has launched with it.
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MRAM stores information magnetically and is non-volatile, so it can retain data when power is interrupted. That makes it a candidate for boot memory: the memory a system relies on to start up. In a spacecraft or defense system, the design concern is not simply whether a memory can hold data; it is whether it can do so predictably in the intended radiation and operating environment, and whether it fits the system’s qualification and integration requirements.
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Avalanche and NHanced say the memory architecture includes error detection and correction (EDAC) on the memory die. Their January announcement says this allows radiation-induced errors to be handled without system resets or data loss. That is a vendor-and-partner claim, not an independent test result established by the announcement. Patti described the requirement more simply to EE Times: “We need something which is hardened.”
What Avalanche means by “Space Grade”
Avalanche describes Space Grade as meeting five requirements together. The January announcement emphasizes three—survive radiation, retain data, and demonstrate flight heritage—while the company’s broader definition also includes endurance and write behavior. The distinction matters: a memory’s being non-volatile alone does not establish that it meets the company’s full space-grade definition.
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- Survive radiation: The memory must tolerate the radiation environment for which it is selected and qualified. Avalanche calls its architecture radiation-immune; that characterization is the company’s claim, not a published dose result for this NHanced integration.
- Retain data for the mission: The data must remain available over the required mission period, including when power is absent. Avalanche describes this as permanent retention, but the announcement does not give a retention duration or conditions for the NHanced design.
- Endure unlimited writes: Avalanche says the memory has unlimited write endurance. The announcement does not provide an independently verified endurance test or a numerical limit.
- Commit writes instantly: Avalanche describes writes as deterministic in nanoseconds. The announcement does not provide a specific timing value, test conditions, or a like-for-like comparison with other memory options.
- Demonstrate flight heritage: The company includes flight heritage in its definition of Space Grade. The partnership announcement does not identify a specific mission or state that this NHanced integration has flown.
These are the vendor’s criteria and product claims; qualification for a particular mission still depends on the parts, package, system design, and mission requirements involved.
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What the 2.5D chiplet approach changes
In the announced approach, the MRAM is a separate die integrated with an FPGA package as a chiplet, rather than being described as memory embedded inside the FPGA itself. NHanced’s hybrid-bonding and 2.5D packaging flows are intended to join those components into a system-in-package. The companies cite potential benefits in size, weight, and power, as well as ruggedness, security, thermal management, latency, and development speed. These are stated goals, not quantified results: the announcement publishes no measured improvement in those areas.
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- Supplier Device Package 8-DFN-EP, Small Flag (5x6)
- Base Product Number MR25H10
- Package / Case 8-VDFN Exposed Pad
- Operating Temperature -40°C ~ 85°C (TA)
- Clock Frequency 40 MHz
The chiplet framing also gives the companies a way to discuss reusing the memory die across advanced packaging designs. It does not, by itself, establish that the same package is suitable for every FPGA, mission, or radiation profile.
How this differs from conventional memory choices
Avalanche’s announcements argue that conventional PROM, SRAM, NOR, and NAND flash options can create system-level bottlenecks in demanding space designs. The material provided for this collaboration does not include independent, like-for-like measurements of those memory types against Avalanche MRAM. The practical comparison is therefore about design priorities, not a quantified winner across all applications.
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- Package / Case 8-VDFN Exposed Pad
- Supplier Device Package 8-DFN (5x6)
- Base Product Number MR25H256
- Operating Temperature -40°C ~ 85°C (TA)
- Write Cycle Time - Word, Page -
| Design question | What the announcements say about Avalanche MRAM | What is not established for this integration |
|---|---|---|
| Data through power loss | MRAM is non-volatile; Avalanche says its Space Grade memory retains data for the mission. | A mission-specific retention duration and test conditions. |
| Radiation behavior | Avalanche calls the architecture radiation-immune and says EDAC is built into the memory die. | A published radiation-dose result or independent comparative test for this design. |
| Write endurance and timing | Avalanche claims unlimited endurance and deterministic nanosecond writes. | Test conditions and direct measurements against PROM, SRAM, NOR, or NAND. |
| Boot-memory role | The January announcement identifies MRAM as boot memory in the rad-hard FPGA system-in-package. | Specific boot-time measurements or a named flight system. |
| Qualification and deployment | Avalanche includes flight heritage among its Space Grade criteria. | Mission identification, qualification status for a particular NHanced package, and deployment schedule. |
That means the announcement supports a design-in rationale—non-volatility plus vendor-claimed radiation tolerance, endurance, write behavior, and heritage—not a universal conclusion that MRAM should replace flash or SRAM in every satellite FPGA. Selection remains an engineering decision based on mission requirements and qualification evidence.
Timeline: from discrete MRAM to package integration
- July 29, 2024: Avalanche announced its enhanced discrete Space Grade-E MRAM family, describing higher radiation-tolerance specifications, increased burn-in, enhanced screening, and pin-compatible migration across Space Grade families.
- January 26, 2026: Avalanche and NHanced announced use of Avalanche Space Grade MRAM as boot memory in a rad-hard FPGA system-in-package for satellite and defense missions.
- February 10, 2026: EE Times reported NHanced President Bob Patti’s account of the selection and the requirement for hardened memory after other evaluated options fell short.
- March 16, 2026: The companies announced a 2.5D integration approach using Avalanche MRAM as a chiplet with NHanced hybrid bonding for rad-hard FPGAs.
Can you buy this MRAM?
This is a business-to-business aerospace and defense design-in, not a retail memory-card product. The announcements do not publish a consumer price, production quantity, customer count, or retail channel. Availability, qualification, and deployment are procurement and engineering matters; a buyer would need to work through the relevant vendor or authorized representative for the requirements of a specific program.
Best Value
Avalanche’s January 2026 company description says it has over 300 patents and applications. That is the company’s own figure, not an independent patent audit, and it does not establish the qualification or availability of this particular NHanced integration.
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