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TSMC launched iRCX on May 27, 2009, as an interoperable format for delivering interconnect-modeling data for its 65 nm and 40 nm process technologies. Developed with electronic design automation (EDA) partners through TSMC’s Open Innovation Platform (OIP), iRCX was intended to help design tools interpret that data consistently across physical-design and electrical-analysis workflows.
What iRCX was designed to do
Interconnects—the wires and other connections within a chip—have parasitic resistance and capacitance that affect performance and power evaluation. Tools need modeling data about those effects to estimate how a design will behave. TSMC’s iRCX format provided a common way to deliver that data between tools, with the aim of improving its integrity and interpretation.
TSMC announced iRCX for its 65 nm and 40 nm technologies. The company identified these workflows as beneficiaries:
- Place and route
- RC parasitic extraction
- Electromigration analysis
- Power-integrity analysis
- Electromagnetic simulation
How TSMC worked with EDA vendors
TSMC presented iRCX as the first of several interoperable EDA interface formats co-developed with design-tool partners through OIP. The company said partners implemented support and that tool accuracy was qualified against silicon measurements. TSMC directed users to its TSMC-Online EDA qualification program for detailed qualification results. A contemporaneous EE Times report also described participation by multiple EDA vendors, but did not provide a complete vendor list.
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In the launch announcement, Shauh-Teh Juang, then senior director of Design Infrastructure Marketing at TSMC, described the effort as a collaboration with multiple EDA vendors to create and qualify an interoperable format for delivering and interpreting data between interconnect extraction, modeling and analysis tools and advanced process technologies.
Which tools support iRCX?
The launch materials establish that EDA partners implemented support, but they do not name a complete list of supported tools or vendors. TSMC pointed to its EDA qualification program for detailed results. The public information cited here therefore does not support a definitive vendor-by-vendor compatibility list.
How iRCX relates to 3Dblox
TSMC introduced 3Dblox in 2022 through its 3DFabric Alliance. The two formats address different design problems: iRCX focused on interoperable interconnect-modeling data, while 3Dblox is a modular format for representing key physical stacking and logical connectivity in 3D IC designs.
| Aspect | iRCX | 3Dblox |
|---|---|---|
| Primary scope | Interconnect-modeling data for TSMC’s 65 nm and 40 nm process technologies at its 2009 launch | Physical stacking and logical connectivity in 3D IC designs, as described by TSMC in 2022 |
| Workflows identified | Place and route, RC parasitic extraction, electromigration, power integrity and electromagnetic simulation | Qualified flows spanning physical implementation, timing verification, physical verification, EMIR analysis and thermal analysis |
| Interoperability aim | Consistent delivery and interpretation of interconnect-modeling data across tools | A modular standard for modeling key aspects of 3D IC stacking and connectivity in one format |
| Qualification information | TSMC said partner tools were qualified against silicon measurements; detailed results were available through its EDA qualification program | TSMC describes qualified flows for the listed analyses; the cited description does not state a silicon-measurement qualification method |
These formats show a continuing interest in coordinating design data across tools, but they are not interchangeable: one addresses interconnect modeling, and the other addresses 3D integration.
Why iRCX matters in context
iRCX was a foundry-and-EDA ecosystem initiative, not a consumer software format. Its significance was the attempt to standardize how interconnect models moved between tools and to qualify the resulting tool behavior against silicon measurements. TSMC’s later work reflects the continued complexity of integration: its 2025 annual-report material says 3 nm SoIC stacking entered volume production in 2025 and describes ongoing CoWoS, SoIC, SoW and BEOL interconnect development. That later activity provides context for the broader engineering challenge, but it does not establish that iRCX itself remains in current use.
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