In Marek Piekarski’s 2001 proposal, the central redesign is to move queues to the switch inputs and use a crossbar coordinated by a global, quality-of-service-aware arbiter. The idea was to make scheduling decisions with a view across the fabric rather than rely on a shared memory or a chain of smaller interconnect stages. It is a useful way to understand the design trade-offs, not a current deployment recommendation: the article’s performance figures and market assumptions are historical.
What does a switch fabric do?
A switch fabric is the internal connection between a device’s ingress and egress processing. An arriving packet reaches an ingress processor, which identifies its destination and traffic treatment; it then crosses the fabric and leaves through the appropriate egress processor. The fabric’s job is to move traffic between those sides while the surrounding system handles such tasks as queuing, quality of service (QoS), and, where needed, packet modification.
Piekarski’s article, republished by EDN on June 1, 2001, frames the design problem around congestion and traffic growth. It characterized traffic as “doubling every 3 to 6 months.” That is the article’s period assessment, not a current traffic-growth measurement.
Why does queue placement change the design?
Output queuing
In an output-queued design, the fabric carries traffic toward the egress side, where it can be queued and shaped for transmission. This arrangement aims to keep the fabric’s contribution to delay small, but it requires the fabric and egress processing to cope with the aggregate traffic directed to an output port.
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Input queuing
With input queuing, traffic waits at the ingress side and the fabric transports cells toward their destinations. The challenge is coordinating which inputs can use the fabric at the same time, while accounting for destination and traffic priority. Piekarski’s proposal addresses that challenge with virtual output queues (VOQs) and arbitration: each input keeps separate queues for destinations and traffic classes, and an arbiter uses queue state, QoS needs, and egress feedback to select connections.
Separating traffic by destination means one input’s waiting traffic is not represented by a single undifferentiated queue. In the article’s design, that queue visibility gives the arbiter a basis for choosing crossbar connections and helps avoid starving egress queues. The source presents this as a scheduling approach, not as a guarantee that every traffic pattern or implementation will avoid delay.
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How do the fabric options compare?
The article compares three broad approaches by where they queue traffic, how they move it internally, and what coordination or scaling burden follows. The figures below are claims made in the 2001 article or its EDN republication, not present-day limits or benchmarks.
| Architecture | Queueing and movement | Trade-off described in the 2001 article |
|---|---|---|
| Shared memory | Packets are placed in shared memory so they can be made available to any egress processor. | Scaling depends on global-memory bandwidth as well as bus width, pin count, packaging, and layout. Piekarski wrote in 2001 that shared-memory fabrics “currently won’t scale beyond 20 Gbps of total line-end bandwidth”; this is a historical design claim, not a current engineering limit. |
| Multistage interconnect network (MIN) | Traffic crosses multiple stages and can use multiple paths; the design involves input queuing. | More stages and paths create additional arbitration and queuing decisions. The EDN republication described about 20% of MIN interconnect as available for line ends and 80% as used to move data internally, and characterized MINs as capable of scaling into tens or hundreds of terabits. Both are period claims from 2001, not verified current specifications. |
| Crossbar | A single-stage, parallel switching medium connects inputs and outputs; the proposal places VOQs at the inputs. | The design depends on arbitration to choose connections from queue state, QoS requirements, and egress feedback. Piekarski argued that a global arbiter could use a whole-fabric view to coordinate those choices. |
What does “reinventing” the crossbar mean in this proposal?
The proposed change is not simply to use a crossbar instead of another fabric. It is to pair a crossbar with input-side VOQs and an arbiter that sees the state of the fabric as a whole. Inputs report which destinations and traffic classes have cells waiting; egress feedback and QoS needs also inform the arbitration. The arbiter then selects which input-to-output connections can proceed.
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Piekarski’s argument was that centralized, whole-fabric arbitration could reduce coordination overhead and make wider use of the crossbar. He wrote, “A global arbiter can eliminate a lot of communication overhead and thus reduce latency by maximizing the width of the pipes in the switch fabric.” The 2001 article claimed better than 97% efficiency for crossbar resources with such an arbiter and gave 20 to 30 ns as an example arbitration-decision interval. Those figures describe the proposal in its original period; they are not modern product measurements or performance guarantees.
The architecture therefore exchanges one set of constraints for another. Shared memory places pressure on global-memory bandwidth and its physical implementation. A MIN introduces internal stages and more arbitration points. An input-queued crossbar requires the arbiter to coordinate requests with enough information about queues, QoS, and egress conditions. The article’s design framework is useful for comparing those burdens, but does not establish which option is best for a present-day system.
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How did the article address different traffic and physical links?
The article also considered combining TDM/SONET traffic with IP/ATM traffic in one fabric. Its proposal included integrating serializer/deserializer (SerDes) functions with fabric ICs and using asymmetric serial links: most link intelligence would sit at one end, while slave-side links could share a phase-locked loop (PLL). Piekarski said this approach could reduce power and die-area demands.
That is a historical design proposal, not evidence about a currently available component or a validated contemporary implementation. The article does not identify a present-day part, compatibility requirement, or deployment in which this asymmetric arrangement should be selected.
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What can a present-day reader take from a 2001 article?
Use the article as an architecture discussion, not a specification sheet. Its most durable contribution for a reader evaluating fabric designs is the set of questions it makes explicit:
- Where do packets wait: at the inputs, at the outputs, or in shared memory?
- Does the fabric rely on access to global memory, parallel crossbar connections, or multiple internal paths and stages?
- How much coordination is needed to match traffic to destinations while respecting QoS?
- What resources and complexity are consumed by internal movement and arbitration?
- What evidence supports a claimed latency, utilization, or scaling figure for the particular system being considered?
The last question matters because the source is an industry architecture article attributed to Marek Piekarski, then manager of systems architecture at Power X Ltd., rather than a current product specification or an independent standards document. It supplies period claims, but does not establish current architecture comparisons, component availability, or best practices. Its numerical claims should be read in that historical context.
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