For a very large SoC, hierarchical signoff can make RTL analysis more manageable: verify blocks and their assumptions in the SoC context, replace implementation detail with carefully constructed abstract models, then analyze those models together with the top-level logic. This divide-and-conquer approach can reduce the cost of chip-level analysis, but it is trustworthy only when the models preserve the information a check needs and their relationship to the RTL is validated.
Why flat RTL signoff can become a bottleneck
A flat flow analyzes the complete integrated RTL for an IP subsystem or SoC. As designs grow, reading and analyzing every implementation detail can consume enough memory and runtime to slow the signoff feedback loop. Atrenta’s 2015 article reported typical SoCs exceeding 100 million gates; for designs around 50 million gates, it gave a typical analysis time of about 1–8 hours, potentially allowing only 1–3 iterations in a workday. These are historical figures from that article, not current benchmarks or a prediction for a particular tool, design, or machine.
The problem is not simply that a large design takes longer to analyze once. Slow runs constrain how often engineers can check changes, investigate violations, and rerun after fixes. A hierarchical method aims to retain the cross-block visibility needed for SoC checks without repeatedly processing all the lower-level implementation detail.
What an abstract model preserves—and what it leaves out
In the divide-and-conquer flow described by Atrenta, block-level analysis first checks constraints and assumptions in the SoC context and generates abstract models. The final SoC analysis then uses those block views alongside the top-level logic, rather than loading every block’s complete implementation for that run.
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The model is not merely a block diagram or a list of ports. The described model retains interface logic, port type and direction, and connected-signal information. That topology can support checks such as detecting combinational loops that cross block boundaries and propagating constants through the SoC. Lower-level implementation detail that those checks do not require is omitted, reducing the analysis burden.
“Abstract model” does not name one universal representation. The information to preserve depends on the signoff question. Connectivity sufficient for a structural check is not automatically sufficient to establish cycle-accurate functional behavior, clock-domain-crossing behavior, or low-power state-transition correctness.
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How to build and run the hierarchical flow
- Define the checks and their required semantics. List the SoC-level questions the run must answer—for example, cross-block connectivity, combinational loops, constant propagation, CDC structure, or low-power behavior. Identify what each check needs to know about interfaces, timing, state, clocks, resets, and power intent. Do not assume a single abstract view covers every check.
- Analyze each block against its intended SoC context. Check the block constraints and assumptions in the environment where the block will operate. Record assumptions about connected signals, clocks, resets, and other conditions relevant to the chosen checks. The Atrenta methodology explicitly places this contextual verification before model generation.
- Generate the abstract views. Preserve the port types and directions, interface logic, and signal connections required for the planned topology checks. For checks that depend on richer behavior, establish what additional state or semantics the model must retain; a topology-only view cannot stand in for them.
- Analyze the assembled SoC view. Run the intended checks over the abstract block views and top-level logic together. This is where cross-boundary paths, connectivity, and other system-level properties can be examined without loading every block’s implementation detail.
- Validate the abstraction and close violations. Check that each abstract model still matches the assumptions and behavior relevant to its use, investigate findings in the owning block and integration context, and rerun after changes to RTL, constraints, assumptions, or models. Keep a traceable relationship between the checked model and the RTL revision it represents.
The last step is essential: a smaller model is not evidence that the result is sound. An omitted behavior may be exactly what determines whether a reported property holds.
Can block-level verification be trusted at SoC level?
It can answer system-level questions when the abstraction retains the semantics those questions require, the blocks’ assumptions hold in the integrated design, and the relationship between abstract views and RTL is justified. A block that passes under an assumption about a clock, reset, or input may not be safe if the SoC violates that assumption. Likewise, a model that hides an implementation behavior can conceal a real cross-boundary problem or make a conclusion appear stronger than the evidence warrants.
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For topology-oriented checks, retained ports and connectivity can expose issues that span otherwise separate blocks. For functional claims, teams need stronger evidence than interface shape alone. Useful evidence can include explicit assumption checks, equivalence or refinement checks, and a defined process for regenerating and reviewing models when RTL changes.
Formal methods for connecting abstract models to RTL
There is a fundamental semantic gap between an untimed electronic-system-level (ESL) model and cycle-accurate RTL. Lucas Deutschmann and co-authors, in their 2024 DVCon paper “Formal RTL Sign-off with Abstract Models,” describe that gap as a barrier to relying on the higher abstraction layer for hardware signoff. An untimed model can express operations without preserving the cycle-by-cycle behavior that RTL implements; treating the two as interchangeable would therefore be unjustified.
Path Predicate Abstraction
The paper presents Path Predicate Abstraction (PPA) as a way to establish a formally sound relationship between abstraction levels for general-purpose designs. The authors also warn that achieving this with PPA can require substantial manual effort. PPA is therefore a soundness technique, not a blanket guarantee attached to any model called “abstract.”
Operation-level synthesis, equivalence, and state refinement
The same paper proposes Operation-Level Synthesis, operational equivalence checking, and automatic state refinement as ways to reduce manual work in relating abstract models to cycle-accurate RTL. These techniques address the model-to-implementation relationship; they do not remove the need to define the property, assumptions, and behavior being preserved.
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Related IEEE work on control-data slicing describes removing information irrelevant to a particular analysis to reduce the state space for model checking and simulation while preserving critical timing behavior. Earlier symbolic-model-checking research likewise uses abstraction, time discretization, and nondeterminism to make RTL verification more tractable for timed heterogeneous systems. These are complementary ideas: reduce the model where safe, while retaining the timing or control facts needed for the property under examination.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How flat, hierarchical, and formal approaches compare
| Approach | Typical scope and preserved information | Evidence and limits |
|---|---|---|
| Flat RTL analysis | Integrated subsystem or SoC RTL; the complete implementation is analyzed. | Atrenta’s 2015 account gives historical scale and runtime figures, but no current comparable benchmark or memory figure. It avoids relying on reduced block views for that analysis, while potentially increasing runtime and iteration cost. |
| Hierarchical abstract-model analysis | Blocks are checked first; abstract views and top-level logic are analyzed together. The Atrenta description preserves interface logic, port type and direction, and connected-signal topology. | Supports topology-oriented checks such as cross-block combinational loops and constant propagation. Soundness depends on contextual assumptions and on the model preserving what each check requires; no universal runtime or coverage figure is stated (Atrenta, 2015). |
| Formal abstraction or refinement | Relates a higher-level or abstract model to cycle-accurate RTL, potentially preserving behavior relevant to functional claims. | The 2024 DVCon paper discusses PPA, operational equivalence checking, and automatic state refinement. It does not establish that every abstract-model flow uses these techniques or provide a universal cost or performance figure. |
| Commercial hierarchical signoff platforms | Product-specific scope and semantics; documented examples include low-power analysis and CDC analysis using hierarchical flows. | Capabilities and performance claims are vendor- and flow-specific. Product-page figures are not universal, independently benchmarked results; the methodology and signoff target must be checked for the intended design. |
Commercial examples: low-power and CDC signoff
Synopsys documents VC LP for low-power signoff at RTL, netlist, and power-gated-netlist stages, with partition, subsystem, and SoC scope. Its product page describes a Signoff Abstract Model methodology. Synopsys advertises up to 10X speedup for VC LP low-power signoff from RTL to power-gated netlist; that is a vendor claim, not an independently established result for every design or flow. The same page quotes Jung Yun Choi, VP at Samsung Electronics, saying the Signoff Abstract Model flow accelerated static low-power verification by 5X for Samsung’s ASIC designs. That is a named customer statement published by the vendor, not a general benchmark.
Synopsys also describes VC SpyGlass CDC as covering structural and functional CDC analysis and supporting hierarchical verification with signoff abstract models. These examples show that commercial abstractions may target distinct signoff semantics: low-power state and power intent are not interchangeable with CDC behavior, and neither should be inferred from topology alone.
What to evaluate before adopting the method
- Scope: Does the flow cover the block, subsystem, and full SoC levels needed for the signoff decision?
- Preserved semantics: Are interface topology, timing, control state, low-power states, CDC behavior, or cycle accuracy represented as required by each check?
- Soundness evidence: Are assumptions checked in the SoC environment? Is there an equivalence, refinement, or other explicit justification linking the model to the RTL?
- Capacity: Measure runtime, memory use, and achievable iteration frequency on the team’s own designs. The historical Atrenta figures and vendor speedup claims are not substitutes for that measurement.
- Coverage: Confirm that the selected flow detects the classes of issue in scope, including cross-block loops, connectivity, constants, CDC, low-power transitions, or functional properties as applicable.
- Debug and governance: Determine how violations map back to RTL, how assumptions and waivers are reviewed, and how model provenance is maintained across design revisions.
- Deployment fit: Check whether the flow supports the actual inputs and stages—RTL-only, netlist, power-gated netlist, or mixed ESL/RTL—used by the project.
Hierarchical analysis is most useful when the whole design is too expensive to reanalyze flat for every question, but it should be treated as a controlled signoff architecture—not as permission to discard implementation behavior without proof. Choose the smallest model that preserves the semantics required for the check, then verify the assumptions and model-to-RTL relationship that make its result meaningful.
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