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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteAutomotive teams need to verify complex chips, software, subsystems and vehicle-level behavior together—and do enough of that work before silicon is committed. Simulation remains useful, but the 2020 account by Mentor Graphics (a Siemens business) argues that simulation alone cannot cover the pre-silicon workload of enormous multicore automotive SoCs in a practical timeframe. Its proposed answer is a verification continuum that combines simulation, hardware emulation and shared evidence across suppliers.
Why automotive verification is becoming harder
Cars increasingly depend on electronics and large volumes of software. At the same time, emissions, fuel-efficiency and safety requirements call for closer integration across vehicle systems. Verification must therefore establish more than whether a chip works in isolation: teams need confidence that electronics and software operate correctly, efficiently and safely as parts of larger systems.
Jean-Marie Brunet, then senior marketing director for Mentor’s Emulation Division, summarized the shared challenge in a 2020 article: “One common theme dominates for all players: the challenge of proving that all of these electronics and their software will run smoothly, correctly, efficiently, and safely.”
More computation, more interactions
Automotive silicon is moving from relatively small ECU chips toward platform system-on-chips (SoCs) with numerous CPUs, advanced protocols, vision systems and AI engines. Those capabilities must fit within acceptable power constraints. Tier 1 suppliers then integrate substantial software stacks, while the chip and its interfaces must work with other components in the subsystem.
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Each added processor, software layer, protocol and component creates another place where assumptions can fail. Verification needs to cover interfaces as well as individual blocks, and it must account for the combinations created by real use cases. At the vehicle level, scenarios may involve the car interacting with other vehicles, pedestrians and other objects, making the test space larger still.
Why simulation alone can leave a pre-silicon gap
Simulation lets teams exercise a design before a physical chip exists, but execution time can become a limiting factor. The 2020 EE Times article reports that on enormous multicore SoCs, simulating even an operating-system boot and low-level-driver activity can take impractically long. That makes it difficult to complete broad verification suites through simulation alone.
The schedule matters because important design changes are cheaper before manufacturing. The article says a complex SoC mask set can cost “in the millions”; it gives no more precise figure. Before mask commitment, a change costs engineering time. Afterward, a design change can require buying another mask set. A verification flow that cannot exercise enough software and system behavior before that decision leaves teams exposed to both technical and economic risk.
Brunet described the limitation this way: “There is a fundamental gap between what is required for full pre-silicon verification and what simulation will allow.” This is a claim about the limits of simulation as the sole method for very large designs, not a claim that simulation has no role.
Simulation and hardware emulation serve different parts of the flow
In the 2020 account, hardware emulation is presented as a way to run larger verification workloads faster while retaining access to design behavior for debugging. PAVE360, Siemens’ cited example, uses Veloce hardware emulation and is described as supporting verification from chip through subsystem to full vehicle. The article does not provide independently measured timings or a like-for-like benchmark, so its speed comparison should be read as a vendor-attributed claim.
| Verification need | Simulation, as described in the 2020 article | Hardware emulation and PAVE360, as described in the 2020 article |
|---|---|---|
| Execution speed | Can be impractically slow for operating-system boot and low-level-driver simulation on enormous multicore SoCs. | Siemens/Mentor said PAVE360 could run verification suites thousands of times faster than standard simulation; the article supplies no benchmark conditions or independent measurement. |
| Design visibility and debug | Not stated by the 2020 article. | The article describes internal visibility and debug capabilities. |
| Running software | The article specifically identifies OS boot and low-level-driver simulation as a time-consuming challenge. | The article presents hardware/software co-verification as part of the environment; it does not specify a supported software list. |
| Chip-to-vehicle coverage | The article says vehicle-level verification suites are computationally challenging; it does not describe a simulation-only coverage range. | PAVE360 is described as spanning individual chips, subsystems and full vehicles, including electromechanical verification through FMI. |
| Interfaces and collaboration | Not stated by the 2020 article. | The environment is described as supporting transaction-level modeling (TLM) for inter-component verification and interoperability with chip and software tools. |
| Hardware/software metrics | Not stated by the 2020 article. | The article says the environment supports co-verification with performance, bandwidth and power metrics. |
| Pre-silicon schedule risk | The article warns that simulation time can prevent complete verification before mask commitment. | The article positions emulation as a way to expand pre-silicon verification; it gives no quantified schedule-risk reduction. |
These methods are complementary rather than interchangeable. Simulation can remain part of the flow; the case for emulation is to make software-heavy and system-level pre-silicon testing practical where simulation throughput is insufficient. The cited article does not establish that emulation removes the need for simulation, guarantees complete coverage or replaces post-silicon checkout.
How to share verification across OEMs, Tier 1s and Tier 2s
Automotive verification is distributed across an ecosystem. Tier 2 suppliers provide chips and components; Tier 1 suppliers integrate those parts with software and other subsystem components; OEMs are responsible for the vehicle-level system. The 2020 article also notes that changing supply-chain relationships—including nontraditional and vertically integrated participants—complicate coordination.
Evidence must therefore travel with the design. A test result at the component boundary is useful only if downstream teams can connect it to the requirements and interfaces they rely on. The following practices follow from the coordination problems identified in the article:
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- Track requirements across boundaries. Record which component or subsystem requirement each test addresses, who owns the evidence and which implementation or interface it covers.
- Verify protocols and interfaces between implementations. Agreement on a protocol name is not enough; teams need evidence that connected implementations behave compatibly in the relevant use cases.
- Make component evidence reusable. Tier 1 and OEM teams should be able to understand and use Tier 2 verification results without losing the context needed to judge their relevance to the integrated system.
- Extend tests into integration. A verified component does not by itself establish that the software stack, neighboring components and vehicle-level interactions work together.
- Keep records tied to the system being assembled. Requirements, test results and configuration details need to remain traceable as components and software are integrated.
The article identifies digital-twin models that mirror individual cars in operation as a possible route to extending verification from chips to complete automobiles. It also acknowledges the practical challenge: executing verification suites at every level is demanding. A useful continuum therefore needs both reusable component-level evidence and tests that exercise system interactions, rather than relying on a single exhaustive vehicle-level run.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What ISO 26262 means for the verification process
The 2020 article describes OEM responsibility for ISO 26262 safety requirements across subsystems, components and the tools used to assemble the final system. It characterizes compliance as requiring extensive planning, testing, documentation and certification. In practice, this makes verification evidence an organizational deliverable as well as a technical one: the OEM must be able to account for the safety work across the components and tools in the vehicle.
The article does not detail specific ISO 26262 clauses, safety integrity levels or prescribed tool-qualification methods, so those should not be inferred from its general description. Teams applying the standard need to determine the applicable requirements for their project and document how their safety activities and evidence address them.
What Siemens PAVE360 is—and what the 2020 account establishes
PAVE360 is presented in the 2020 Mentor/Siemens and EE Times coverage as a chip-to-vehicle verification environment built around Veloce hardware emulation. The described capabilities include TLM-based inter-component verification, FMI-based electromechanical verification, internal visibility and debug, interoperability with chip and software tools, and post-silicon checkout. The article also describes hardware/software co-verification with performance, bandwidth and power metrics.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →These are product and performance claims made in 2020, including the claim that suites can run thousands of times faster than standard simulation. The cited material does not establish present-day product availability, current feature sets, supported integrations, pricing or benchmark conditions. Organizations evaluating PAVE360 should verify those details with Siemens for the specific product version and project.
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