Some Armv7-A processors support 40-bit physical addressing and hardware virtualization, but that does not mean every processor called “ARM7” does. Cortex-A7 is a documented example: Arm specifies both capabilities for it. The 40-bit figure applies to physical or intermediate-physical addresses—not to the virtual addresses used by ordinary ARMv7-A software.
What does “ARM7” mean here?
“ARM7” commonly refers to older Arm processor cores, while 40-bit addressing and hardware virtualization in this context are later Armv7-A capabilities. Cortex-A7 is an Armv7-A processor, not a blanket example of what every older ARM7 core can do. Arm’s Cortex-A7 product information explicitly lists 40-bit physical addressing and enhanced hardware virtualization for that implementation.
So the useful question is whether a particular processor implements the relevant Armv7-A extensions—not whether its name contains “ARM7.” Arm’s ARMv7-A engineering overview describes LPAE as extending physical addresses to 40 bits and the Virtualization Extension as providing hardware support for hypervisors and multiple guest operating systems.
What does 40-bit addressing cover?
In this architecture, LPAE (Large Physical Address Extension) extends the physical-address space to 40 bits. That represents 240 bytes: 1 TB in decimal units, or 1 TiB when expressed as a binary capacity. It is an address-space limit, not a promise that a processor, board, or system has that much installed memory.
Do these 3 things before closing this tab:
1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errors#1 Best Overall
- High-performance foundation line, ARM Cortex-M4 core with DSP and FPU, 512 Kbytes Flash, 180 MHz CPU, ART Accelerator, Dual QSPI
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
The 40-bit capability is not a 40-bit virtual-address space. ARMv7-A’s VMSA (Virtual Memory System Architecture) supports virtual addresses up to 32 bits. With virtualization, a guest’s stage-1 translation can produce an intermediate physical address (IPA); the hypervisor’s stage-2 translation then maps that IPA to a physical address (PA). Thus, a guest can use the usual 32-bit virtual-address model while the system manages a wider physical address space.
How do the two translation stages work?
- Guest stage 1: VA to IPA. The guest operating system’s translation maps a virtual address (VA) to an IPA. When Virtualization Extensions are in use, a non-secure PL1&0 stage-1 table can output an IPA rather than a final PA.
- Hypervisor stage 2: IPA to PA. The separate stage-2 regime applies hypervisor-controlled mappings to translate the IPA to the final PA. This second stage is what lets the hypervisor control how guest-visible memory maps onto physical memory.
The hypervisor control plane is at PL2. VTTBR points to the stage-2 translation tables, and VTCR controls the stage-2 translation regime. HTTBR and HTCR define the non-secure PL2 stage-1 regime; they are distinct from the stage-2 controls.
Rank #2
- Ultra-low-power with FPU ARM Cortex-M4 MCU 80 MHz with 1 Mbyte Flash, LCD, USB OTG, DFSDM
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
How do short-descriptor and long-descriptor tables differ?
“40-bit” alone does not tell you the mapping granularity. The ARMv7-A/R Architecture Reference Manual distinguishes short-descriptor and long-descriptor formats as follows:
| Format | Address space and granularity | What that means |
|---|---|---|
| Short descriptor | 32-bit PA space at 4 KB granularity; optionally, 40-bit PA space at 16 MB granularity | A short-descriptor setup can retain 4 KB mappings within a 32-bit PA space, or use a wider PA space with much coarser 16 MB sections. |
| Long descriptor (LPAE) | Full 40-bit IPA or PA space at 4 KB granularity | The long-descriptor format supports 4 KB granularity across the full 40-bit IPA or PA space. |
The distinction matters when reading architecture or platform documentation: 40-bit physical reach and fine-grained mappings are not interchangeable claims. With virtualization, the long-descriptor format can describe the 40-bit IPA space used between the guest’s stage 1 and the hypervisor’s stage 2.
Rank #3
What does Cortex-A7 establish—and what does it not?
Cortex-A7 is a concrete Armv7-A implementation. Arm lists LPAE, hardware virtualization, Neon, and a 128-bit AMBA 4 AXI interface among its capabilities, and states that Cortex-A7 provides 40-bit physical addressing and enhanced hardware virtualization.
That establishes support in the Cortex-A7 design; it does not establish that every product built around a Cortex-A7 exposes the full theoretical address space, includes sufficient memory, or can boot an arbitrary hypervisor and guest operating systems. Those depend on the processor configuration, SoC and board limits, interrupt-controller integration, and software support. Architectural capability should not be mistaken for a guarantee about a particular device.
Rank #4
- Mainstream Mixed signals MCUs ARM Cortex-M4 core with DSP and FPU, 512 Kbytes Flash, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Can be powered from USB.
- Three LEDs, Two Push-buttons
- Support of wide choice of Integrated Development Environments (IDEs) including IAR, ARM Keil, GCC-based IDEs
What should you check on a specific processor or board?
Use the processor and SoC documentation, rather than the family name alone, to verify the implementation. The important checks are:
- Virtualization Extensions and PL2: confirm that the processor implements hardware virtualization and exposes the hypervisor mode needed by the intended software.
- LPAE and descriptor format: check for 40-bit PA/IPA support, the table format in use, and the mapping granularity the system requires.
- Stage-2 translation: verify the stage-2 controls and the relevant translation and TLB behavior for the processor and hypervisor.
- Interrupt virtualization and GIC integration: check the processor and platform documentation for the interrupt-controller features required by the intended guests.
- Actual memory limits: compare the processor’s addressing capability with the SoC’s MMU and cache configuration, memory controller, board design, and installed RAM.
- Software compatibility: confirm that a hypervisor and each intended guest operating system support that processor and platform.
Is 40-bit ARM the same as 64-bit ARM?
No. “40-bit” here describes the width of physical or intermediate-physical addresses available through LPAE. ARMv7-A remains a 32-bit architecture with virtual addresses up to 32 bits; a 40-bit physical-address capability does not turn it into a 64-bit instruction-set architecture or imply a 64-bit virtual-address space.
Recommended Free Tools
Quick Recap
Best Value
- STM32F103C8T6 ARM STM32 minimum system development module.
- ST-Link V2 support the full range of STM32 SWD interface debugging, simple interface (including power supply), 4 line speed, stable work.
- Use the current smart phones of Mirco USB interface, easy to use, USB communication and power supply can be done.
- The board lead to all the I/O resources.Download with SWD debug interface, which requires a minimum of 3 wires to complete debug a download task
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
