Efficient NVRAM algorithms must make updates durable in the right order—not merely visible to other threads—and provide a recovery protocol for writes that can be interrupted. Start by defining the failure model and recovery invariant, then choose a failure-atomic update pattern, place flushes and fences where that invariant requires them, and test recovery under interrupted updates.
Define what must survive a failure
Before choosing instructions or optimizing, specify which failures the algorithm must handle: power loss, a process crash, a machine reset, or a media error. These are not interchangeable assumptions. Also state the persistence domain the program relies on, including whether its design assumes ADR or eADR, DAX, or a PMDK abstraction. The durability guarantees and ordering rules available to the algorithm depend on those choices.
Write down the recovery invariant in concrete terms. For example: after recovery, a record must be either the complete old value or the complete new value, never a mixture. Then identify the commit point—the point after which recovery is allowed to treat the update as committed—and specify which data and metadata must already be durable at that point.
Keep visibility separate from durability
A store becoming visible to another thread does not mean it has reached a failure-protected domain. Intel’s 2020 Persistent Memory FAQ explains that writes need a flush and a fence to ensure they are in such a domain. Therefore, ordinary thread synchronization alone is not a persistence protocol: the algorithm needs both the ordering needed by concurrent readers and the persistence operations needed by recovery after a failure.
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Source-code order is not enough to prove persistence order. Caching and out-of-order execution can allow data to become persistent in an order different from the order in which the program issued stores. Put flushes and fences at dependency boundaries, and document what is guaranteed durable after each one. The useful question is not “Did this store execute first?” but “Can recovery observe the dependent state before the data it depends on is durable?”
Choose an update pattern that can recover from interruption
On x86, Intel’s 2020 FAQ describes power-fail atomicity guarantees for stores as only eight bytes; larger updates can tear. Intel’s write-ahead-logging guidance likewise says that larger updates need a higher-level mechanism. Do not assume a multi-field record, pointer structure, or metadata update is indivisible just because it is one logical operation in the program.
| Pattern | How it handles interruption | What to account for |
|---|---|---|
| Undo or redo logging | A log records information needed to restore the old state or apply the new state during recovery. | Define when the log is durable, how recovery distinguishes a complete log entry from a torn one, and when log space can be reused. |
| Copy-on-write with a durable commit marker | Write a new version separately and make it authoritative only through a commit marker that recovery can validate. | Ensure the new version is durable before the marker can be accepted; make marker validation and cleanup safe after an interruption. |
| Transaction abstraction | A transaction facility supplies a higher-level mechanism for grouping updates and recovery. | Understand the abstraction’s persistence and failure guarantees, and include its metadata and overhead in performance measurements. |
SNIA’s work on atomics and transactions addresses atomic updates, and PMDK provides transaction and pool facilities. These are design options, not substitutes for stating the invariant: the application still needs to know what constitutes a committed update and what recovery must validate.
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Order writes, flushes, and commit markers
A typical durable-update dependency can be expressed as a timeline. It is a pattern to adapt to the chosen persistence domain and API, not a universal instruction sequence:
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- Flush the cache lines containing the data. Identify every line that carries data required by the update.
- Fence at the dependency boundary. Do not allow the commit step to be treated as durable before the data it depends on.
- Write the commit marker or equivalent metadata. Design it so recovery can distinguish a valid committed state from an interrupted or torn one.
- Flush and fence the commit metadata as required. Recovery may accept the new state only when both its data and its commit indication satisfy the persistence protocol.
Intel describes memory as accessed in 64-byte cache lines in its 2019 introduction. That makes line coverage important: a logical record may touch more than one line, and flushing one line does not establish that unrelated lines are durable. Track which lines each update dirties and which of them must be durable before commit.
Use the appropriate cache-line persistence instruction
Intel’s 2020 Persistent Memory FAQ distinguishes the relevant instructions by behavior: CLFLUSH writes back and invalidates a line; CLFLUSHOPT permits more parallel flushing but is weakly ordered and requires SFENCE; CLWB writes a line back while leaving it valid. The right choice depends on the processor support and the persistence interface the program targets.
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Do not scatter instruction choices through application logic if a supported PMDK facility or portability layer can express the needed persistence operations. That keeps the algorithm’s recovery protocol distinct from platform-specific implementation details and makes it easier to adapt the code when the target persistence domain changes.
Reduce persistence overhead without weakening the proof
Flushes and fences have costs, but removing one is safe only if the recovery invariant still holds for every interruption point. Optimize the dependency graph rather than deleting operations by intuition:
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- Avoid redundant flushes. Do not flush the same unchanged or already-covered data repeatedly unless the protocol requires it.
- Coalesce adjacent dirty lines. Organize data so a logical update touches fewer persistence units where practical.
- Separate frequently updated metadata. Aligning such metadata to cache-line boundaries can reduce unintended sharing of lines with unrelated data.
- Place fences only at proven dependency boundaries. A fence can be removed or moved only after verifying that no crash can expose dependent state before its prerequisites are durable.
Intel’s persistence-inspection tooling can detect redundant flushes and fences, as well as out-of-order persistent stores. Treat those findings as prompts to review the protocol, not as permission to remove an operation without rechecking recovery correctness.
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Account for DAX, allocation, and persistent references
DAX and memory mapping can expose byte-addressable persistent memory without the page-cache copies associated with block-style access. That does not eliminate the need for durable allocation metadata, recoverable pointer relationships, torn-update handling, or restart validation. The SNIA NVM Programming Model describes operating-system behavior intended to let applications and other software use NVM capabilities; the application still has to maintain its own data-structure invariants.
Intel’s 2020 FAQ notes that non-DAX block-style access can move an entire 4 KiB block even when a single byte changes. Thus, byte-addressable access and block-oriented I/O have different update costs and failure considerations. For persistent structures, also decide how references will remain valid after restart; allocation and recovery design are part of the algorithm, not incidental setup.
Validate recovery and measure complete durable commits
Functional tests show that an update works when it runs to completion; they do not prove that persistence ordering is correct. Test interrupted updates at meaningful points in the write, flush, fence, and commit sequence, then verify the recovery invariant for every resulting state.
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- Use PMDK facilities where applicable, including its pool and transaction support.
- Use Intel Persistence Inspector to look for persistence-order issues and redundant flushes or fences.
- Use pmemcheck, pmempool, and pmembench where applicable to check persistent-memory behavior, pools, and performance.
- Test restart validation, partially persisted metadata, torn-record detection, and cleanup after recovery—not just successful commits.
When comparing algorithms, record failure-atomicity scope, flush and fence count, dependency depth, recovery time, write amplification, cache-line locality, concurrency control, portability across persistence domains, metadata overhead, and proof complexity. Benchmark throughput and tail durability latency, and state the hardware, supported instructions, dataset size, concurrency, and recovery cost. Separate volatile execution time from the latency of a complete crash-safe commit; a faster update path is not necessarily a faster durable update.
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