To verify an ACE cache-coherent system with UVM, check more than AXI transactions: model cache-line state and data ownership, create competing accesses from the relevant masters, observe snoop and maintenance behavior, and verify what each master and memory may legitimately observe. The exact plan depends on the ACE generation, enabled features, interface roles, and system topology.
ACE extends AXI4 with hardware-coherence behavior, including five cache states, extra signaling on existing channels, and additional channels for communication with cached masters. UVM provides a reusable SystemVerilog verification methodology; it does not define ACE behavior or prescribe a particular testbench architecture.
What should an ACE UVM testbench prove?
Arm defines coherence in terms of observations: “Regions of memory are coherent if writes to the same memory location by two components are observable in the same order by all components.” The practical verification question is therefore whether masters observe architecturally correct data and ordering—not whether every cache or memory always contains the newest value. See the Arm AMBA AXI and ACE Protocol Specification, IHI 0022H.
In particular, a store requires one authoritative copy at the relevant point in the protocol, but later accesses can cause new cached copies to be obtained. Main memory need not reflect the newest data while a cache still holds a dirty copy. Arm’s Issue H specification requires memory to be updated before no cache holds a copy; a scoreboard that assumes write-through behavior can report false failures.
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Which protocol and system configuration are you verifying?
Before writing sequences or reference-model rules, record the actual design contract. ACE-family interfaces and ACE-Lite do not offer identical coherence behavior, and a plan for one revision or topology should not silently be treated as valid for another.
- Identify the exact ACE generation and specification revision, plus the transaction, snoop, barrier, DVM, and maintenance features the design implements.
- Document each interface role: coherent ACE masters, ACE-Lite managers, interconnect or other relevant components, and which agents can issue or receive snoops.
- Map coherent address ranges, cache-line size, number and type of participating masters, and any regions with different attributes or behavior.
- Specify allowed outstanding transactions, response timing and interleaving constraints, reset assumptions, and the completion conditions the design promises.
- Set the simulator, SystemVerilog, UVM library and API baseline, along with coverage goals and verification exit criteria.
These are project inputs, not values that can be inferred from the protocol name. The specification describes protocol behavior; it does not prescribe a UVM architecture.
How should the scoreboard represent cache coherence?
Use a reference model indexed at least by cache line, tracking data knowledge and the protocol-relevant state of each participating cache. Keep observed bus transactions, snoop outcomes, and modeled architectural data distinct enough to diagnose whether a failure is a channel violation, a state/ownership error, or an incorrect data observation.
Arm IHI 0022H names five states. The table summarizes their verification significance; it is not a substitute for the selected revision’s precise transition and transaction rules.
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| State | Verification interpretation |
|---|---|
| Invalid | The cache does not hold a valid copy of the line. |
| UniqueClean | A unique copy is held by one cache and is clean; no other cache may hold a copy. |
| UniqueDirty | A unique copy is held by one cache and is dirty; it is the authoritative modified copy. |
| SharedClean | The line is clean and may be held in more than one cache. “Shared” is not proof that another cache still has a copy. |
| SharedDirty | Shared copies exist under the protocol’s dirty-sharing rules; modified data must still have one dirty owner. |
Two modeling details prevent common false failures. First, Unique status means only one cache may hold the line, while Shared state can persist in one cache after another cache discards its copy without notifying peers. Therefore, do not equate a Shared state with observed proof of two current copies. Second, enforce dirty ownership and the protocol’s memory-update conditions rather than requiring memory to match a dirty cache at every instant.
How can a reusable UVM environment separate the checks?
A practical environment can use per-interface agents, passive monitors that publish observed channel and transaction activity, sequences that generate controlled competing accesses, a cache-line reference model and scoreboard, and protocol assertions. This is an engineering arrangement, not a UVM or Arm-mandated structure.
- Check legal protocol behavior. Use revision-appropriate assertions and monitors for channel handshakes, response and snoop sequencing, and other enabled protocol rules. Avoid asserting behavior for unsupported features.
- Update the reference model from observations. Track requests, snoop responses, data transfers, cache-line state knowledge, and memory visibility according to the selected specification and DUT contract.
- Check architectural outcomes separately. Compare data returned to each master and visible at memory only when the protocol and operation’s completion condition make that observation meaningful.
- Preserve transaction context in failures. Report the line address, initiating and responding agents, relevant prior state, request, snoop result, and expected versus observed data or visibility.
Separating protocol legality from coherence/data correctness helps distinguish a malformed channel interaction from a validly transported transaction that nevertheless produced the wrong system-level observation.
Which traffic scenarios expose coherence bugs?
Sequences should create state changes and meaningful observations, with timing variation that remains legal for the selected revision. Use the design’s actual address map and line size rather than hard-coding assumptions from a generic ACE example.
- Read sharing: Have one master read a cold line, then have another master read the same line. Check returned data and the resulting shared-copy knowledge without assuming that a later Shared state proves both copies remain present.
- Stores from unique and possibly shared states: Store to a line held uniquely, then test a line that may be shared. Check required notifications or snoops and verify that subsequent readers observe the architecturally correct value.
- Competing accesses: Interleave reads and writes from multiple masters to the same line, vary response timing, and exercise outstanding traffic within the target’s legal transaction rules. Check ordering and observations at all relevant participants.
- Dirty transfer and eviction: Exercise intervention, dirty-line transfer, eviction, and writeback paths. Do not require memory to contain the newest value while a dirty cache copy remains; check memory update at the protocol-defined point.
- ACE-Lite paths: Test I/O-coherency scenarios separately from fully coherent ACE-master cases. The one-way snoop visibility means symmetric assumptions about who can snoop whose cache are unsafe.
- Ordering and system operations: Include barriers, DVM, or cache maintenance only when the target revision and implementation support them. Arm Issue H notes that barriers are not supported on ACE5 and ACE5-Lite interfaces.
How should cache maintenance expectations differ by operation?
Maintenance checks must reflect the selected operation, domain, implementation support, and precise completion condition. Arm Issue H distinguishes these outcomes:
| Operation | Expected effect to verify |
|---|---|
| CleanShared | Clean cached copies and make associated writes observable. |
| CleanInvalid | Write dirty data to memory, invalidate copies, and make writes observable. |
| MakeInvalid | Invalidate copies; dirty data might be discarded. |
Do not apply a single generic “maintenance completed, therefore memory has the newest data and all copies are gone” rule to every operation. Check the operation-specific effect and the specification’s completion semantics for the implemented configuration.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What functional coverage demonstrates meaningful exercise?
Plan coverage against the configured system and its reachable behaviors, not just a list of transaction names. Useful functional dimensions and crosses include:
- Pre-state × request type × snoop response × post-state.
- Unique or shared and clean or dirty dimensions, alongside the number of participating coherent agents.
- ACE versus ACE-Lite path, intervention or data source, and relevant ownership-transfer cases.
- Maintenance operation × completion or visibility outcome, for operations implemented by the target.
- Legal response and timing variation under outstanding traffic, where supported by the interface contract.
Coverage goals are project recommendations, not items mandated by Arm. If illegal-transition stimulus or assertion-failure bins are used to show checker activation, keep those metrics distinct from functional coverage and assertion pass/fail status.
How do ACE-Lite, ACE5, and CHI change the plan?
ACE-Lite provides one-way I/O coherency: ACE Managers maintain cache coherence for ACE-Lite Managers, while other Managers cannot snoop ACE-Lite Manager caches. Model that directionality explicitly rather than treating an ACE-Lite port as a fully symmetric coherent cache participant. Arm’s AMBA 4 overview describes ACE and ACE-Lite.
Arm’s current AMBA specifications index marks the AMBA ACE Protocol Specification as superseded by CHI. The AMBA 5 overview discusses ACE5 as an extension aligned with CHI and describes CHI as the coherent hub interface. CHI is not simply another ACE revision. Verification remains relevant for designs built to ACE-family interfaces; for a new architecture, first establish whether the target is ACE, ACE5, or CHI before reusing a plan.
Which UVM baseline should the project use?
Accellera describes UVM as a standard intended to support reuse of verification environments and VIP, with a SystemVerilog class-library reference implementation. Its UVM Community page describes that purpose. The Accellera UVM download page lists “UVM 2020-3.2 Reference Implementation” with a modified date of 2026-08. That listing is release metadata, not evidence of compatibility with every simulator. Confirm the library, supported APIs, and IEEE 1800.2 and tool baseline used by the project before making portability claims.
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