For glitch-free clock switching, use a clock-specific mux or switching primitive supported by the target device—not an ordinary logic mux—and follow its documented control timing and clock-activity requirements. The safe choice depends on whether the inputs are related or independent, whether both clocks remain active during handoff, and how much switching delay the design can tolerate.
Why an ordinary mux can glitch
A clock drives state changes in sequential logic, so an unintended edge or shortened pulse can trigger logic at the wrong time. A plain combinational mux can change its output as soon as its select input changes. If its clock inputs are at different logic levels, that change may create a malformed pulse. A data mux is therefore not automatically safe to use on a clock path.
Clock-specific switching structures control when the new clock is allowed through. Altera’s clock-multiplexing guidance describes a structure that enables a new clock only after the other clock is inactive. In the example described, the outgoing clock must continue for at least a few cycles; stopping it immediately can prevent the handoff from completing.
Choose a switching method for the target hardware
There is no universal glitch-free mux circuit with the same guarantees across FPGA families and external clock devices. Start with the exact part’s clocking resources and documentation, then check the conditions that apply to your clock relationship and control signals.
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- Wide Range of Digital Levels:Digital 3V to 20V
- Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD-VEE = 18V
- High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD-VEE = 18V
- Binary Address Decoding on Chip
- 100% Tested for Quiescent Current at 20V
| Option | Documented use and conditions | Handoff timing |
|---|---|---|
| AMD Versal BUFGCTRL | AMD describes it as a synchronous/asynchronous glitch-free 2:1 mux. CE0 and CE1 have setup/hold requirements; violating them could cause a clock glitch. See AMD BUFGCTRL documentation. | Not stated in the cited documentation summary; consult the exact device documentation. |
Altera ipm_cdc_glitchless_clk_mux |
Supports related or unrelated clocks according to the CLK_TYPE setting. Misclassifying unrelated clocks as related may cause a glitch. Both clocks must be toggling before and after the select change for switching to complete. See Altera macro documentation. |
For related clocks, the macro waits for the next falling edge of each clock; for unrelated clocks, it waits for the second falling edge of each. |
| Microchip PolarFire NGMUX | Supports dynamic glitch-free switching between independent clocks. The published behavior is specific to PolarFire. See Microchip PolarFire documentation. | With both clocks active, Mode 0 is documented to take up to three current-clock cycles plus three new-clock cycles. Mode 1, for a current clock that is inactive or uncertain, is documented to take up to 50 new-clock cycles with a minimal chance of glitch. |
| Renesas 580-01 external clock mux | Renesas describes the part as switching between two clock sources without glitches or short pulses. Verify electrical compatibility and detailed timing in the current product datasheet. See Renesas 580-01 product page. | Consult the current datasheet for the exact timing. |
Design checks before switching
- Identify the exact device. Confirm the FPGA family or clock-mux IC and use its supported clocking resource. A primitive from another family may not have the same placement, behavior, or guarantees.
- Classify the clock relationship. Determine whether the sources are related or unrelated according to the vendor’s definition. For the Altera macro, set
CLK_TYPEaccordingly; configuring related clocks when the sources are unrelated may allow a glitch. - Check enable and select timing. Follow the setup/hold requirements for each control pin. AMD explicitly warns that failure to meet BUFGCTRL’s CE timing requirement could result in a clock glitch.
- Keep clocks active when required. The Altera macro requires both clocks to toggle before and after a select change. The generic Altera structure also needs the outgoing clock to continue for at least a few cycles in the described example. Do not assume a handoff will complete if a source stops at the request.
- Allow for the handoff interval. A glitch-free transition is not necessarily immediate. Determine the applicable worst-case timing for the selected primitive and mode, and ensure the surrounding system can tolerate the resulting clock pause or transition interval.
- Review reset and CDC behavior separately. A source or frequency change can affect reset sequencing and clock-domain crossings, but the cited vendor material does not establish one reset or CDC recipe that applies to every design.
Can you switch between unrelated clocks?
Some device-specific solutions explicitly support independent clocks, but that does not make every clock mux safe for arbitrary inputs. Microchip documents PolarFire NGMUX for independent clocks, while Altera’s parameterized macro supports related and unrelated clocks only when configured for the correct relationship. AMD BUFGCTRL’s documented control requirements must also be met. Check the exact primitive’s support and timing rather than inferring behavior from another family’s implementation.
What if one clock stops during the handoff?
Stopped-clock behavior is primitive-specific. Altera’s macro requires both inputs to be toggling before and after the select change, so a stopped source can prevent switching from completing. PolarFire NGMUX documents a separate Mode 1 for cases where the current clock is inactive or uncertain, with a stated bound of up to 50 new-clock cycles and a minimal chance of glitch. That Mode 1 behavior is a PolarFire-specific guarantee, not a general property of clock muxes.
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How to choose between FPGA logic and an external mux IC
For an FPGA design, first evaluate the target family’s dedicated clock-switching resources: their placement, supported clock relationships, control timing, activity requirements, and handoff delay. An external clock mux IC may suit a board-level source switch, but verify the part’s electrical interface, supported frequencies, and detailed timing against the system requirements. The Renesas 580-01 is one documented example; its product description alone is not enough to establish suitability for a particular circuit.
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