A silicon photonics foundry fabricates photonic integrated circuits (PICs) using a defined process and usually provides a process design kit (PDK) so customers can design for that process. To choose one, first confirm that its current PDK supports the devices and integration your product needs. Then compare prototype access, performance evidence, manufacturing maturity, design support, packaging and test, and written commercial and qualification terms. A provider’s public capability page is a starting point—not proof that its process fits a particular design.
What is a silicon photonics foundry?
It is a manufacturing provider for photonic integrated circuits: chips that guide, modify, generate, or detect light using integrated optical components. A foundry’s fabrication process determines which components and combinations can be made. Its PDK connects that process to the design workflow by specifying process rules, component libraries, models, and verification resources.
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For example, AIM Photonics describes its PDKs as including design guides, design-rule-checking decks, component libraries, and tools or scripts for creating prototypes for its wafer services. GlobalFoundries describes PDKs as process models, rules, and libraries used by electronic design automation (EDA) tools. The practical point is that a PDK is process-specific: a PIC layout is not automatically portable between foundries.
What a foundry relationship can include
Depending on the provider and platform, the offer may extend beyond wafer fabrication to prototype access, design or IP services, packaging, assembly, and test. For instance, imec describes platform access through dedicated full-mask runs and, for selected technologies, multi-project wafers (MPWs), as well as design and IP services and PIC supply-chain management. GlobalFoundries describes packaging, assembly, and test services, while AIM Photonics’ Assembly Design Kit (ADK) brings supported packaging constraints and verified components into design workflows.
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How do I choose a silicon photonics foundry?
Start with the product’s required devices and system conditions, not the foundry’s headline process name or wafer size. Use the following checks to narrow the candidates, then get project-specific answers from each provider.
1. Match the device set and integration
List the functions the PIC must perform: for example, passive waveguides and filters, modulators, detectors, silicon nitride routing, lasers, or electronic-photonic integration. Check whether the current PDK supports every required device in the needed combination. A process name alone does not establish support for a particular component or integration route.
Platform menus vary. imec describes silicon and silicon nitride (SiN) options and integration routes involving III-V lasers, semiconductor optical amplifiers, and lithium niobate modulators. Those are specific platform capabilities, not standard features shared by every silicon photonics foundry. Ask for the exact process and PDK documentation that applies to your design.
2. Compare performance at your operating point
Translate system requirements into the quantities the process must meet: operating wavelength, optical loss, bandwidth, modulation format, detector performance, filter response, and any other application-specific limits. Ask the provider which values are measured, demonstrated, qualified for production, or still development targets, and under what conditions they were obtained.
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GlobalFoundries’ technology page reports support up to 100G/λ for Gen 1, says Gen 2 is proven up to 200G/λ, and describes a path to 400G/λ for Gen 3. It also reports athermal CWDM filter results of <1 dB insertion loss, <0.2 dB passband ripple, and <-30 dB crosstalk, with performance described as design dependent. These are GF’s own platform claims, not independent cross-foundry benchmarks; validate the specific performance needed for your design with the provider.
3. Establish how you can prototype
Ask whether the relevant process is available through an MPW run, which shares a wafer among multiple designs, or whether the project needs a dedicated full-mask run. Confirm eligibility, submission dates, design constraints, expected fabrication turnaround, and what deliverables the prototype service includes. imec documents full-mask access and MPW access for selected iSiPP200 technologies; its page does not establish one universal schedule or price.
4. Check production maturity and capacity
Compare the wafer diameter and production status of the exact process you plan to use, alongside capacity, process control, and the supplier’s scaling plan. Wafer size is not a substitute for information about yield, availability, or allocation. For example, Tower Semiconductor’s November 26, 2024 announcement introduced a standard 300 mm silicon photonics offering and described its 200 mm PH18 platform as in high-volume production at that time. imec separately describes mature 200 mm iSiPP200 and a 300 mm platform. These dated provider statements do not guarantee current capacity, a customer’s allocation, or yield; confirm the status and terms directly.
5. Treat packaging and test as part of the PIC design
Before choosing a process, define how light and electrical signals enter and leave the product. Check fiber attach and optical coupling, electrical interfaces, package constraints, test access, assembly flow, and the plan for identifying known-good die. These choices can constrain the PIC layout, so they should not be left until after the chip design is complete.
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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteAIM Photonics’ ADK supports specified wirebond and fiber-attach configurations and includes templates, verified design data, and multiphysics simulation. GlobalFoundries describes several fiber-attach approaches along with packaging, assembly, and test capabilities. Confirm that the particular package and test flow your product requires is supported—not merely that packaging is offered.
6. Verify the design environment and support
Check the exact PDK version, supported devices, model coverage, design rules, verification decks, supported EDA tools, licensing conditions, access requirements, and update policy. Confirm that the provider can support the team’s reference flow and that its engineering support matches the project’s needs. Synopsys lists a multi-provider photonic PDK ecosystem and says PDKs can be obtained from the selected foundry; that does not mean a general EDA-tool license automatically includes access to a specific foundry PDK.
7. Get project-specific commercial and qualification terms in writing
Ask each shortlisted provider for terms covering non-recurring engineering (NRE) and mask costs, wafer pricing, minimum volumes, lead times, capacity reservation, yield definitions, process-change control, IP protection, data handling, failure analysis, and product qualification. The public provider pages cited here do not establish comparable current values for those terms. Do not infer them from wafer diameter or marketing claims.
What do the public provider examples establish?
The providers below illustrate different publicly described capabilities; they are not a ranking. Their pages do not provide a common specification set or independently comparable customer outcomes.
| Provider | Publicly described offering | What to verify for your project |
|---|---|---|
| AIM Photonics | Lists PDK entries for active/passive, low-loss, silicon nitride, quantum-flex, and electronic-interposer use cases, among others; connects PDKs to wafer fabrication services. Its page marks some other kits “Coming Soon.” An ADK announcement describes packaging design enablement. | Confirm the exact kit’s availability and version, device support, wafer-service route, and compatibility with the required package. |
| GlobalFoundries | Describes a production silicon photonics portfolio, PDK and reference-flow support, photonics/RF/advanced-packaging integration, and support for pluggable optics and co-packaged optics. | Validate vendor-published device and performance claims against the design’s operating conditions; confirm the applicable process, packaging flow, and production terms. |
| imec | Describes 200 mm and 300 mm silicon photonics platforms and 200 mm and 300 mm SiN options. Its iSiPP200 description includes a validated PDK, potential active-component integration, and full-mask and selected MPW access. | Check which technology supports the needed devices and integration, whether its MPW route applies, and the current schedule and access conditions. |
| Tower Semiconductor | Announced a standard 300 mm silicon photonics offering on November 26, 2024, alongside its 200 mm PH18 platform, which the announcement described as in high-volume production at that time. | Ask Tower to confirm the current status, PDK and device fit, capacity, and terms for a new design. |
How do I get a silicon photonics prototype made?
- Define the PIC requirements. Document the device set, integration needs, operating conditions, package, electrical interfaces, and test requirements.
- Request the applicable PDK information. Obtain the current PDK version and documentation, including supported components, models, rules, verification resources, EDA compatibility, and access terms.
- Select the prototype route. Ask whether the needed process is open to an MPW run or requires a dedicated full-mask run; confirm eligibility and the actual schedule with the provider.
- Design and verify for that process. Use the foundry’s PDK and design rules, and include packaging constraints in the layout where the provider’s flow supports them.
- Agree on fabrication, packaging, and test deliverables. Establish in writing what is fabricated, assembled, measured, and returned, along with the schedule, cost, and criteria for evaluating the prototype.
What should a useful foundry comparison record?
For each candidate, keep evidence tied to the specific platform and PDK rather than treating a company-level capability as universal. Record the following before making a selection:
- Required devices and integration, plus the exact PDK version and its EDA and licensing conditions.
- Performance evidence at the target wavelength and operating conditions, marked as measured, demonstrated, qualified, or a development target.
- Prototype route, access eligibility, submission window, design constraints, and fabrication turnaround.
- Wafer diameter, production status, capacity and allocation terms, and process-change controls.
- Package, fiber attach, assembly, and test compatibility with the product’s interfaces and qualification plan.
- Written commercial terms, yield definitions, IP and data protections, and support arrangements.
For a deeper grounding in the design side of this decision, Cambridge University Press publishes Silicon Photonics Design: From Devices to Systems by Lukas Chrostowski and Michael Hochberg. The publisher describes coverage of design, simulation, testing, fabrication, foundry-ready designs, and PDK use. It was published in 2015, so use current provider documentation for present-day process details: Cambridge University Press book page.
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