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What still limits quantum computing after error rates improve? Lower physical error rates help, but they do not by themselves make a quantum computer useful. The machine must also protect logical information with manageable overhead, perform reliable logical gates, decode error signals fast enough, and scale its hardware and control systems to run a complete algorithm within a realistic resource budget.

Why better physical error rates are not the whole story

A physical qubit is a device-level component; a logical qubit is information encoded across multiple physical qubits and protected through repeated measurements. Those measurements, called syndrome measurements, reveal clues about errors so the system can correct them without directly measuring the encoded information.

Lower physical error rates can make error correction more effective. But the practical test is whether the resulting logical errors become rare enough across the full computation. Errors can accumulate during gates, measurements, storage, and communication, so a low error rate for one physical operation does not guarantee a low failure probability for a long algorithm.

In a 2024 Nature study, the authors describe physical error rates of 10-3 to 10-2 per operation in the hardware levels discussed in their framing. They give about 10-12 logical error probability per operation as an illustrative target for factoring a 2,000-bit number. That is a workload-specific example, not a universal threshold: different applications can demand very different levels of reliability and resources.

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Error correction has an overhead cost

Protecting a logical qubit requires more than assigning several physical qubits to it. The system must repeatedly measure the code, process the resulting data, and apply corrections. These operations consume physical qubits, gates, classical computation, and time. How much they cost depends on the error-correcting code, hardware noise, and the reliability the target computation requires.

The National Academies’ 2019 report, Quantum Computing: Progress and Prospects, gives an illustrative estimate of roughly 15,000 physical qubits to encode a logical qubit for certain fault-tolerant workloads under its stated assumptions, including a starting error rate of 10-3. This is an older, assumption-dependent example, not a current universal qubit count.

Logical gates add another hurdle

A protected memory can preserve encoded information, but computation requires operations on that information. A practical fault-tolerant machine needs a useful set of logical gates, including universal computation. Some gates—especially non-Clifford gates—can require additional fault-tolerant techniques, such as magic-state methods or code switching, adding resource and scheduling costs.

That is why a memory demonstration and a computationally capable machine are distinct milestones. A system must show that it can carry out the needed logical operations reliably, not only keep a logical state intact.

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New codes aim to reduce the cost, not eliminate the problem

Researchers are exploring codes that may protect information with less overhead than conventional approaches in some settings. A 2024 Nature paper, High-threshold and low-overhead fault-tolerant quantum memory, presents a low-density parity-check approach and identifies encoding efficiency as a key scaling concern. It is a research result, not proof that a general-purpose, low-overhead architecture is solved.

The decoder must keep up with the processor

Error correction produces streams of measurement outcomes that a classical decoder must interpret. If decoding is too slow, the quantum processor may have to wait, or the system may fail to maintain correction at the required pace. Decoder accuracy matters too: it must infer errors reliably from noisy data rather than from idealized measurements.

Real devices can also exhibit leakage—when a qubit leaves the computational states used by the design—and crosstalk, where operations affect neighboring qubits. These effects can create error patterns that are harder to handle than simplified noise models suggest.

The 2024 Nature study Learning high-accuracy error decoding for quantum processors reports progress in decoding experimental surface-code data. Its authors also identify remaining work on scaling decoders, achieving hardware-relevant throughput, and extending the approach from memory experiments to logical operations. In other words, demonstrating accurate decoding on a particular dataset is not the same as proving that a decoder can support a large computation in real time.

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Scaling the hardware depends on the architecture

Adding qubits is not simply a matter of repeating the same component indefinitely. Each platform has its own constraints on the physical devices, their connections, and the systems needed to control and read them. A 2024 paper on modular connections for error-corrected qubits describes examples of such constraints:

  • Trapped ions: motional-mode crowding can complicate scaling.
  • Superconducting systems: cryostat size and chip fabrication are among the engineering concerns.
  • Rydberg arrays: laser power and field of view are examples of scaling constraints.

These are platform-specific engineering challenges, not universal ceilings. The modular-systems work considers connecting error-corrected modules over noisy links as one way to approach device-size constraints; such links introduce their own reliability and integration requirements.

Control and readout are part of the resource budget

Qubits need systems that can deliver control signals and collect measurements. As a machine grows, the electronics, wiring, power, heat, and physical space involved can become important constraints. A 2024 IEEE review of cryogenic CMOS control discusses power per controlled qubit and the challenges of cryogenic and room-temperature electronics. The appropriate control approach depends on the hardware platform; no single electronics solution applies to every quantum computer.

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What progress should be measured instead?

Raw qubit count or a single physical error figure cannot show whether a computer can complete a useful workload. A more informative comparison looks at the whole path from hardware to computation:

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  • How do logical error rates change as code size increases?
  • How many physical qubits and error-correction cycles are needed per logical qubit or gate?
  • Which logical operations are supported, and can the system perform universal computation?
  • Can the decoder maintain accuracy and throughput under realistic noise?
  • How well do qubits connect within a device or across modules?
  • Can control and readout scale without making power, speed, or integration impractical?

These measures help distinguish an encouraging component-level result from an end-to-end system capable of running a target algorithm. The available evidence does not establish an apples-to-apples ranking of current vendors or hardware platforms across these measures.

Does this mean quantum computers have no near-term uses?

No. Near-term heuristic algorithms and error mitigation are distinct from large, fault-tolerant computations, and their possible uses should be judged on their own merits. In its 2024 review Assessing the Benefits and Risks of Quantum Computers, the NIST-listed authors write: “We discuss how near-term heuristic algorithms and error mitigation, two trends in the research literature, may enable useful and practical quantum computing in the near future.” The same review identifies fault-tolerant algorithms as the primary cryptographic threat. That distinction matters: a possible near-term application does not mean a machine can already run the large fault-tolerant algorithms relevant to cryptographic risk.

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