Short answer: 130nm, 28nm, and 7nm are process-generation labels, not reliable measurements of every transistor feature. Moving between generations can bring higher transistor density, different transistor structures, and new power and performance options—but the label alone does not tell you how fast, efficient, inexpensive, or physically small a finished chip will be.
What does a process-node number mean?
A process node names a generation of semiconductor manufacturing technology. It should not be read as the exact length of every transistor gate, or as a single measurement shared by every feature on a chip. Intel explains why its node naming is not a direct measurement of a transistor dimension in its technology and process-node overview.
For a meaningful comparison, identify both the foundry and the specific process variant—for example, TSMC N7 rather than “7nm” in the abstract. Vendors’ labels do not establish that their processes have identical dimensions, transistor designs, or capabilities.
What changed from 130nm to 28nm to 7nm?
130nm: device choices and trade-offs mattered
In a 2003 technical discussion of its 130nm and 90nm processes, TSMC noted that device characteristics were no longer straightforward extensions of earlier generations. The work highlights the need to select devices and manage trade-offs, particularly in mixed-signal design, where digital logic must coexist with circuits such as analog interfaces. In other words, even at 130nm, a node was not one uniform transistor geometry or a guarantee of a particular circuit result. TSMC’s 130nm and 90nm research overview
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28nm: high-k/metal gate and a range of design targets
TSMC’s 2011 paper on its 28nm high-performance mobile SoC process describes high-k/metal-gate technology and a broad range of power-to-performance options. That is a specific TSMC process and mobile-SoC context, not a description of every 28nm process or chip. TSMC says its logic processes remained planar until FinFETs entered production at 16nm in 2014. TSMC’s 28nm research overview
7nm: TSMC N7 uses FinFETs
TSMC’s N7 is a FinFET process; TSMC says it entered volume production in 2018. That date describes TSMC N7, not every process that a company labels “7nm.” TSMC’s 7nm technology page
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A FinFET’s channel is formed in a fin, with the gate controlling it from multiple sides. Compared with planar structures at short gate lengths, this provides improved electrostatic control. It also gives designers additional choices for optimizing power and performance; it does not by itself dictate the finished chip’s result. TSMC’s 28nm research overview
Does a smaller process node make a chip faster or more power-efficient?
Not automatically. A newer process can enable higher density or different power/performance trade-offs, but the outcome depends on the chip’s architecture, implementation, operating conditions, and design targets. A chip designed for low power may make different choices from one designed to maximize performance, even when both use the same process.
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TSMC’s 2025 Annual Report provides one vendor-specific illustration. Its normalized die-size comparison assigns 1 to 55nm, 0.48 to 40nm, 0.25 to 28nm, 0.11 to 16FFC/12FFC, 0.047 to 7nm, 0.035 to 5nm, and 0.026 to 3nm. For its normalized total-chip-power comparison, it assigns 1 to N55LP at 1.2V, 0.6 to N40LP at 1.1V, 0.3 to N28HPM at 0.9V, 0.07 to 16FFC/12FFC at 0.8V, 0.034 to 7nm at 0.75V, 0.022 to 5nm at 0.75V, and 0.015 to 3nm at 0.75V.
TSMC says it realigned the logic/SRAM/I/O ratio for these comparisons. The figures are normalized comparisons among selected TSMC processes, not a promise that any arbitrary 7nm design will use a fixed fraction of the area or power of any arbitrary 28nm design. The report does not include a 130nm point. TSMC 2025 Annual Report
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What should you compare instead of the node number?
- Foundry and process variant: “TSMC N7” is more informative than an unqualified “7nm.”
- Transistor architecture: Planar and FinFET structures have different channel-control characteristics and design options.
- Density and die area: Ask what is being measured and whether the comparison uses the same kind of design.
- Power and performance under stated conditions: Voltage, workload, architecture, and design goals affect the result.
- Process-specific design constraints: Device choices, available libraries, and manufacturing rules shape what designers can implement.
A process label can help place a technology in a foundry’s roadmap, but it cannot substitute for these details when comparing actual chips.
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