A 10BASE-T1L MAC-PHY lets a processor without an Ethernet MAC connect to a single-pair Ethernet link through SPI. It combines the media access controller (MAC) and physical-layer transceiver (PHY) in one component, avoiding the need for the host to provide a separate MAC interface such as MII, RMII, or RGMII. Analog Devices’ ADIN1110 is one example; whether this architecture is the right fit depends on the host, power budget, performance target, software, and deployment requirements.
Why a conventional Ethernet PHY may not work with a low-power processor
A conventional PHY handles physical signaling on the cable, but it expects a MAC elsewhere in the system. The processor must either include that MAC or connect to a separate MAC device through an Ethernet interface. The 2021 Analog Devices comparison names MII, RMII, and RGMII as interfaces used between a host MAC and a PHY.
Many low-power microcontrollers do not include an Ethernet MAC. A PHY alone therefore cannot provide them with Ethernet connectivity: there is no host MAC interface to drive it. Adding a separate MAC or selecting a processor with an integrated MAC may be possible, but either choice affects component count, board design, software, and power.
What the MAC-PHY changes
A MAC-PHY integrates the MAC with the PHY and presents a serial peripheral interface (SPI) to the host. The processor sends and receives Ethernet frames over SPI rather than using MII, RMII, or RGMII. This makes the architecture useful when the chosen processor lacks an Ethernet MAC, or when adding Ethernet to an existing design that has a suitable SPI port.
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The host still needs networking software and must manage its interface to the device; integration does not remove all packet handling or make the component a plug-in Ethernet adapter. The benefit is that the MAC function no longer has to be built into the processor or supplied as a separate host-side component.
When to choose a MAC-PHY or a separate PHY
| Design consideration | MAC-PHY over SPI | Separate PHY |
|---|---|---|
| Host capability | Fits a processor without an integrated Ethernet MAC, provided it can communicate over the required SPI interface. | Fits a host with an integrated MAC and a supported MII, RMII, or RGMII interface. |
| Processor selection and reuse | Can expand processor choices or let a design reuse a processor that lacks a MAC but has SPI. | Can suit a higher-performance host that already has a MAC and existing MAC drivers. |
| Power assessment | May allow a lower-power processor choice; assess the complete system rather than treating the MAC-PHY’s component power as total consumption. | Compare the complete design, including host and interface requirements. |
| Network handling and timing | Integrated filtering, priority queues, statistics, and timestamp functions may reduce some host-side work. Confirm support in the device documentation and software stack. | Host-side capabilities depend on the MAC, PHY, and software selected. |
| Application constraints | Check SPI throughput, software support, link requirements, diagnostics, and any safety or certification needs. | Check host MAC compatibility, PHY interface support, link requirements, and applicable approvals. |
The choice is architectural, not simply a comparison of chip power figures. A MAC-PHY is especially relevant when the processor has no MAC; a separate PHY is a natural alternative when a suitable host MAC already exists and performance or reuse favors that arrangement.
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What ADIN1110 provides
Analog Devices describes the ADIN1110 as a low-power, industrial 10BASE-T1L Ethernet MAC-PHY compliant with IEEE 802.3cg-2019. Its current product page identifies it as recommended for new designs and lists a four-wire SPI connection. The same page specifies 42 mW in dual-supply operation at 1.0 V peak-to-peak. That is a component figure under the stated operating condition, not the power consumption of a complete Ethernet system.
The product page also lists 16 MAC address filters, high- and low-priority queues with a 28 kB buffer, diagnostics, and IEEE 1588 timestamp support. These functions can matter when a host has limited resources or the application needs traffic prioritization or timestamping. Their practical benefit depends on how the hardware features are exposed and supported by the host software.
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Reach figures require particular care. The current ADIN1110 product page lists reach up to 1,700 m and identifies 1.0 V/2.4 V modes. The April 1, 2021 Analog Devices article instead says up to 1,000 m at 2.4 V peak-to-peak and describes reduced distance at 1.0 V peak-to-peak. These figures come from different source revisions and should not be treated as interchangeable guarantees. Check the current data sheet for the selected mode, cable, and deployment conditions.
How to evaluate the design before choosing
- Check the host interfaces. Confirm whether the processor has an integrated Ethernet MAC. If not, determine whether it provides a suitable SPI interface and whether that interface can meet the application’s traffic and software requirements.
- Compare complete-system constraints. Include the processor, MAC-PHY or PHY, power supplies, memory, isolation or protection components, and software. Do not infer system-level savings from the ADIN1110’s 42 mW component specification.
- Verify required MAC-PHY functions. Check the current data sheet and software documentation for filtering, queue behavior, statistics, IEEE 1588 timestamp support, diagnostics, and the exact host integration model.
- Validate the link conditions. Confirm the required distance, transmit mode, cable characteristics, and applicable standard requirements against current product documentation. Do not use a headline reach figure as a design guarantee.
- Review certification and hazardous-area requirements. ADI discusses intrinsic-safety suitability and programmable transmit levels, but a chip feature does not certify a finished system. Assess the complete design against the approvals and safety requirements for its intended deployment.
- Check implementation resources. ADI’s product page provides access to samples, an evaluation-board request route, a current data sheet, and a user guide dated April 16, 2025. Confirm the exact package, part variant, regional availability, and documentation revision for the intended design.
How ADIN1110 differs from the ADIN1100 PHY option
The 2021 Analog Devices comparison presents the ADIN1100 as a separate PHY option with MII, RMII, or RGMII host interfaces, while the ADIN1110 uses SPI and integrates the MAC. The article reports 39 mW for ADIN1100 and 42 mW for ADIN1110, but does not elaborate the ADIN1100 figure’s operating conditions. Those are dated article values, not a like-for-like current system comparison; consult current data sheets before using them to select a part.
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For a processor without an Ethernet MAC, the interface distinction is the key point: ADIN1110’s integrated MAC supports a host connection over SPI, while the separate-PHY architecture requires a MAC and compatible Ethernet interface elsewhere in the design.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Understanding 10BASE-T1L claims in context
In its 2021 article, Analog Devices describes 10BASE-T1L as full-duplex, point-to-point signaling using PAM-3 at 7.5 MBd with 4B3T coding, and discusses 1.0 V and 2.4 V peak-to-peak modes. Treat those details as the article’s technical framing; for a product design, verify the applicable requirements and operating conditions in the current data sheet and relevant standard documentation.
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The ADIN1110 is an engineering component, not a consumer-ready Ethernet adapter. Its value is the option to connect a MAC-less processor to 10BASE-T1L through SPI, provided the host software, link design, power budget, and deployment approvals all fit the application.
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