Advanced AI chips are difficult to scale because making a tiny pattern is only one step in producing a reliable chip. Lithography, materials, etch, inspection, process control, and packaging must work together across thousands of repeated features and manufacturing steps. A scanner can resolve a fine image without the resulting wafer producing enough working dies for high-volume manufacturing.
Why can’t manufacturers scale AI chips simply by shrinking designs or buying more machines?
Scaling means producing more usable chips consistently—not merely drawing smaller transistors or installing additional equipment. Each wafer passes through a long sequence of tightly coupled processes. A small variation in one step can affect later steps, and defects across repeated structures can make a die fail its requirements.
Yield is the share of manufactured dies that meet the required specifications. At advanced dimensions, pattern variation and defects matter because so many extremely small features must be formed reliably across a 300 mm wafer. The sources cited here do not establish a general yield percentage for advanced AI chips; a single number would also depend on the specific product and manufacturing process.
Manufacturers therefore treat yield as a process-control challenge. TSMC describes using intelligent fault detection and classification, diagnosis, learning, and AI-based equipment and process controls as part of its yield and quality improvement approach. The company describes management spanning front-end wafer processing through packaging. This is TSMC’s account of its approach, not independent evidence of a particular yield level.
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Why is a resolved lithography image not the same as a manufacturable feature?
Lithography projects a pattern onto a light-sensitive resist, but the projected image is only the beginning. Exposure changes the resist; development defines a pattern; and etch transfers that pattern into underlying films. Resist and underlayer behavior, hard masks, etch conditions, and process variation all influence the final dimensions, roughness, and defect rate.
Imec distinguishes the optical resolution limit from the resolution that can yield industry-relevant structures. Its 2025 technical article says the yield-relevant limit for High-NA EUV structures will be larger than a 16 nm pitch, and identifies stochastic defect mitigation as continuing work. In other words, an optical demonstration does not by itself show that a process can make the feature consistently, transfer it through the stack, and produce working dies at volume.
What does High-NA EUV change—and what remains difficult?
Extreme ultraviolet (EUV) lithography uses light with a 13.5 nm wavelength. High-NA EUV raises the scanner’s numerical aperture from 0.33 to 0.55. Imec describes that as a 67% increase and reports that 16 nm-pitch single-print images were demonstrated in 2024. These are research results, not proof that all relevant layers or products are already being made at volume with High-NA.
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Higher numerical aperture can improve resolution and reduce the need for multiple patterning in relevant cases. But the gain must be balanced against process constraints and integrated with the rest of the manufacturing flow. Imec identifies depth of focus, stochastic defects, and stitching among the challenges. Manufacturers also have to develop compatible masks, materials, metrology, inspection, etch integration, and design methods.
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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstall| Approach | What the cited sources establish | Important qualification |
|---|---|---|
| 0.33-NA EUV | Reference numerical aperture for the comparison in imec’s 2025 article. | The cited material does not provide a directly comparable production-yield or throughput figure. |
| 0.55-NA High-NA EUV | Imec reports a 67% higher numerical aperture than 0.33 NA and 16 nm-pitch single-print images demonstrated in 2024. | These demonstrations do not establish broad high-volume use. Yield-relevant resolution is less aggressive than the optical limit, and process integration challenges remain. |
The comparison is about what the cited evidence supports, not a ranking of current manufacturing options. Evaluating a lithography approach also requires looking at exposures and masks needed, defect control, throughput and dose, depth of focus, overlay and stitching, materials compatibility, and the cost and complexity of integrating it into a production process. The cited sources do not provide enough independent data to rank options globally.
Why do masks and materials affect yield?
A mask carries the pattern that the scanner projects, while the resist and other films help define and transfer it. Variability or defects in these materials and processes can reduce pattern fidelity and affect dimensions and alignment on the wafer. As features shrink, these details become manufacturing variables rather than secondary supplies.
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TSMC’s 2025 annual report describes EUV mask development for A14 and beyond. The company reports work on mask-blank materials, multi-beam writer resolution, mask-process conditions, and electron-beam inspection and repair. TSMC says those efforts improved critical-dimension uniformity, pattern fidelity, and overlay accuracy, while reducing mask defects to improve wafer yield and productivity. These are the company’s reported results for its own development work.
Why are equipment demonstrations not the same as production readiness?
A high-volume process needs more than a capable scanner. It needs a coordinated ecosystem of equipment and suppliers, including mask production, resist and underlayers, metrology, inspection, computational correction, and etch integration. Measurements and inspection must identify variation and defects; process controls must then help keep the line within acceptable limits.
In a June 2024 announcement, ASML and imec described a joint lab built around a prototype TWINSCAN EXE:5000 scanner, process and metrology tools, and access for chipmakers and suppliers to develop use cases. The work covered scanner optics and stitching as well as resist and underlayers, masks, metrology, inspection, imaging strategy, computational correction, and etch integration. The announcement anticipated a 2025–2026 timeframe for high-volume manufacturing. That was a forecast made in 2024; the sources cited here do not verify broad High-NA deployment today.
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Why is packaging part of scaling AI chips?
Wafer fabrication is not the whole production problem. AI accelerators can depend on combining compute dies and memory with high-bandwidth connections. Those components must be integrated into a package that meets the product’s electrical, thermal, and physical requirements.
TSMC’s 2025 annual report describes CoWoS as a 2.5D advanced-packaging service and reports strong growth linked to AI demand since 2023. It also describes SoIC wafer-level 3D stacking and related integration for AI and high-performance computing. These examples show why scaling includes advanced packaging as well as transistor processing; they do not establish a market-wide comparison of packaging capacity.
When comparing packaging approaches, relevant considerations include interconnect density and bandwidth, power, die and package size, integration complexity, qualification, and production availability. The cited sources do not provide sufficient independent data to rank those approaches across the market.
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What does “scaling” require in practice?
It requires a manufacturing chain that works as a system. Lithography must create a usable image; masks and materials must preserve its fidelity; etch must transfer it; inspection and metrology must detect problems; and process control must keep results consistent. The resulting dies then need packaging and integration suited to the product.
High-NA EUV illustrates the distinction between promising capability and production readiness: its research demonstrations show what the optics can resolve, while yield, defects, process integration, and packaging determine what manufacturers can deliver reliably. The sources cited here explain those mechanisms and company-specific developments, but do not establish current global bottleneck rankings, specific AI-chip yields, a complete supply-chain constraint map, or broad High-NA production deployment.
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