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ASML’s High-NA EUV scanners keep the 13.5 nm wavelength used by earlier EUV systems but raise numerical aperture (NA) from 0.33 to 0.55. That optical change gives the EXE platform an ASML-specified 8 nm resolution, potentially allowing chipmakers to print some difficult patterns in fewer exposures. High-NA is an imaging capability, not a chip-node name—and its use depends on process economics and manufacturing readiness, not resolution alone.
What High-NA EUV changes
Extreme ultraviolet (EUV) lithography uses light with a wavelength of 13.5 nm to transfer patterns onto a photoresist-coated silicon wafer. ASML’s EXE platform changes the optical system that focuses this light: it increases numerical aperture, or NA, from 0.33 in its NXE EUV systems to 0.55 in EXE High-NA systems. The wavelength stays the same.
NA describes how much light an optical system can collect and focus. A higher NA can resolve finer details, but it also changes the practical demands of imaging and manufacturing. ASML specifies 8 nm resolution for EXE, compared with 13 nm for NXE. Those are scanner resolution specifications—not process-node names or a promise that every feature on a finished chip will be that size.
| Comparison | NXE EUV | EXE High-NA EUV |
|---|---|---|
| Numerical aperture | 0.33, per ASML product information accessed in 2026 | 0.55, per ASML product information accessed in 2026 |
| Stated scanner resolution | 13 nm, per ASML product information accessed in 2026 | 8 nm, per ASML product information accessed in 2026 |
| Exposure field | Reference field size | Half the NXE field, according to ASML’s 2024 explanation |
| Reticle imaging | Conventional reduction arrangement | Anamorphic: 4× demagnification in one direction and 8× in the other, preserving traditionally sized reticles |
ASML’s EXE:5000 product information also claims 1.7 times smaller printable features, 2.9 times higher transistor density, and 40% more imaging contrast than its NXE comparison. These are supplier-stated system comparisons, not guaranteed outcomes for every chip design or manufacturing process.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteHow an EUV scanner prints a pattern
- Generate EUV light. ASML describes firing two CO2 laser pulses at fast-moving tin droplets. The tin is vaporized and emits EUV light.
- Guide the light with mirrors. EUV is absorbed by ordinary materials, including air and glass, so the scanner uses reflective optics rather than conventional transmissive lenses.
- Reflect the mask pattern. Light is directed onto a patterned reflective mask, also called a reticle. The optical system reduces and projects that pattern onto the wafer.
- Expose resist on the wafer. The wafer is coated with a light-sensitive resist. After exposure, the resist is developed; the resulting pattern guides later etching or deposition steps that form device structures.
Why the optics are anamorphic
Raising NA required larger projection optics and introduced challenges at the angles used to reflect EUV from the mask. ASML’s EXE design uses anamorphic optics, which reduce the reticle pattern by different amounts in two directions: 4× in one and 8× in the other. This supports high-resolution imaging while retaining traditionally sized reticles.
The tradeoff is a field half the size of an NXE exposure field. Covering a wafer therefore requires more exposure fields, creating a productivity challenge. ASML says EXE uses faster wafer and reticle stages to address it.
Why chipmakers may adopt High-NA selectively
Fewer patterning steps on difficult layers
The main manufacturing opportunity is to print some especially fine patterns in one exposure instead of combining multiple patterning steps. In principle, fewer steps can shorten process cycle time and reduce opportunities for defects, potentially improving the economics of continued scaling. ASML and imec describe these as potential benefits; they do not mean every layer or product will see the same savings.
The rest of the process must be ready
A scanner is only one part of a patterning process. Imec identifies work on resists and underlayers, photomasks, metrology, imaging strategies, optical proximity correction, and the integration of patterning with etch. These materials and process steps must work together with the optics to produce patterns that meet manufacturing requirements.
Higher NA also narrows the depth of focus—the range over which the image stays acceptably focused. Imec’s technical interview says depth of focus is expected to be two to three times smaller than with 0.33 NA EUV. Thinner resist films are one response, but the tighter process window raises demands on materials, overlay, metrology, and process control.
Productivity figures need a date and context
ASML’s January 2024 explainer stated a figure of 185 wafers per hour and described 220 wafers per hour in 2025 as a roadmap target. The sources available here do not establish 220 wafers per hour as a currently achieved production result. The smaller exposure field, stage performance, uptime, and process qualification all matter when judging productivity; a roadmap target is not the same as demonstrated output.
What adoption evidence shows as of October 7, 2026
| Date and organization | Reported milestone | What it establishes |
|---|---|---|
| July 15, 2026 — ASML | ASML reported that Intel Foundry was using a High-NA EUV process option on selected Intel 18A layers for a subset of Core Ultra Series 3 processors, code-named Panther Lake. ASML described this as a production-environment readiness milestone. | Selected-layer production use had been reported. It does not establish that all 18A layers, or the industry generally, had moved to High-NA. |
| September 7, 2026 — Intel Foundry and ASML | The companies reported more than one million wafers processed to date in a cumulative High-NA processing milestone. | This is a joint reported total, not necessarily the output of a single scanner. |
| March 18, 2026 — imec | Imec announced the arrival of an ASML EXE:5200 in its Leuven 300 mm cleanroom and anticipated full qualification by Q4 2026. | The arrival was announced; the stated qualification date was an expectation, not evidence that qualification had been completed by October 7. |
Imec’s High-NA lab in Veldhoven provides a development environment where chipmakers and suppliers can work on process integration before inserting the technology into production fabs. This kind of ecosystem work matters because adoption involves qualifying masks, materials, metrology, and process flows—not just installing a scanner.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to interpret “High-NA,” “resolution,” and “node”
- High-NA describes the scanner’s higher numerical aperture: 0.55 for EXE, versus 0.33 for NXE.
- Resolution is a stated imaging capability of the scanner. It does not directly name the dimensions of every transistor or wire on a chip.
- Process node is a chipmaker’s technology-generation label. It is not interchangeable with scanner resolution.
- Production readiness can mean different milestones, from tool installation and qualification to selected-layer manufacturing use or broad high-volume deployment. The Intel report concerns selected-layer use, not universal adoption.
High-NA is not a wholesale replacement for existing EUV or deep ultraviolet (DUV) systems. ASML says NXE and DUV tools will remain in use alongside EXE because different layers and process steps call for different lithography approaches. The practical decision is where High-NA’s finer imaging can simplify a particular patterning flow enough to justify its integration and operating demands.
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