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EUV lithography improves how tiny circuit features are patterned on a silicon wafer; advanced packaging improves how separately fabricated dies are connected and integrated into a finished package. They address different parts of chip manufacturing, so they are complementary rather than competing alternatives.
What does EUV lithography improve?
Extreme ultraviolet (EUV) lithography is used during wafer fabrication to transfer circuit patterns onto silicon. ASML says its EUV systems use light with a wavelength of 13.5 nm, which it describes as close to the X-ray range. The process helps form smaller and denser features within an individual die.
That is a patterning improvement: EUV affects the structures made on the wafer, not the later assembly of multiple dies. It does not connect finished chips to one another. ASML’s EUV lithography systems overview explains the technology and wavelength.
What High NA EUV figures mean
In a 2024 explainer, ASML says its High NA EUV systems can print transistors that are 1.7 times smaller and achieve 2.9 times higher transistor density than its NXE systems. These are ASML’s comparisons against that stated system baseline; they are not claims that a finished chip will be 1.7 times faster or deliver 2.9 times the performance. ASML’s High NA EUV explainer provides the comparison.
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What does advanced packaging improve?
Advanced packaging is used to assemble and integrate dies after they have been fabricated. It connects multiple dies or chiplets—sometimes built for different functions or with different process technologies—into one package. Depending on the design, the dies may sit beside one another or be stacked.
These approaches are commonly described as 2D, 2.5D, or 3D integration. They can increase die-to-die interconnect density and let designers combine components without putting every function on one monolithic die. The specific connection method and resulting trade-offs depend on the package design; “advanced packaging” does not mean one universal structure.
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TSMC’s 3DFabric portfolio includes chip-on-wafer and wafer-on-wafer stacking. In a 2020 company blog post, TSMC described 3DFabric as enabling denser 2D, 2.5D, or 3D interconnect configurations for integrating compute cores and chiplets. That is TSMC’s description of its platform, not a universal performance guarantee. See TSMC’s Advanced Packaging Services and its 3DFabric overview.
A company-reported packaging example
Intel says its Data Center GPU Max Series SoC uses EMIB 3.5D packaging and has more than 100 billion transistors, 47 active tiles, and five process nodes. These figures describe Intel’s product example, not a general specification or benchmark for advanced packages. Intel’s packaging terminology and example appear on its Advanced Packaging Innovations page; related company facts are in its Intel Foundry fact sheet.
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How EUV and advanced packaging differ
| Comparison | EUV lithography | Advanced packaging |
|---|---|---|
| Manufacturing stage | Wafer fabrication, while circuit patterns are exposed onto silicon | Assembly and integration, connecting fabricated dies in a package |
| What it improves | Pattern resolution and the ability to form smaller, denser features within a die | Die-to-die connections, integration of multiple dies, and package-level system design |
| Typical result | More intricate transistor and circuit patterns on an individual die | A package combining chiplets or dies, potentially with different functions or process technologies |
| Related terms | EUV, High NA EUV, lithography, patterning | 2.5D, 3D, chiplets, die stacking, heterogeneous integration, interposer or bridge |
| What it does not do | Connect separate finished dies into one package | Print transistor patterns on a wafer or make EUV unnecessary |
Which approach matters for a chip?
That depends on the design challenge. EUV is relevant when the goal is to pattern dense circuitry within a die. Advanced packaging is relevant when the design calls for integrating multiple dies, connecting them at the package level, or combining dies made for different roles or process technologies. A product may use both: lithography patterns its individual dies, and packaging later joins selected dies into a system.
When comparing packaging designs, examine whether their dies are arranged laterally or stacked, the density and length of their connections, package footprint, thermal and manufacturing constraints, and production maturity. The cited company examples do not provide a head-to-head performance ranking for particular packages, and neither technology guarantees a fixed improvement in finished-chip speed, cost, or energy use.
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What current production examples establish
TSMC’s 2025 annual report says that its 3 nm SoIC stacking entered volume production in 2025. This is a company-reported status for that technology and year, not a statement that every advanced-packaging method or 3 nm package is at the same production stage. See TSMC’s 2025 annual report, Chapter 5.
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